Capacitance to code converter with sigma-delta modulator

• US 20080111714A1
• Filed: 11/14/2006
• Published: 05/15/2008
• Est. Priority Date: 11/14/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kremin, Viktor
• Granted Patent: US 8,547,114 B2
• Time in Patent Office: Days
• US Class Current: 341/33
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: H03M 11/02 Details

Abstract

An apparatus and method for converting a capacitance measured on a sensor element to a digital code. The apparatus may include a switching capacitor as a sensor element of a sensing device, and a sigma-delta modulator coupled to the sensor element to convert a capacitance measured on the sensor element to a digital code. The switching capacitor is in a feedback loop of the sigma-delta modulator. The method may include measuring a capacitance on a sensor element of a sensing device using a sigma-delta modulator, and converting the capacitance measured on the sensor element to a digital code.

Claims

1. A method, comprising:

measuring a capacitance on a sensor element of a sensing device using a sigma-delta modulator, wherein the sensor element is a switching capacitor in a feedback loop of the sigma-delta modulator; and

converting the capacitance measured on the sensor element to a digital code.

2. The method of claim 1, further comprising switching the switching capacitor in the feedback loop using an output of the sigma-delta modulator.

3. The method of claim 1, wherein measuring the capacitance on the sensor element comprises:

charging the capacitance on the sensor element on a line coupled to one end of the switching capacitor; and

measuring the capacitance on the sensor element on the line coupled to the one end of the switching capacitor.

4. The method of claim 1, wherein the digital code is proportional to the measured capacitance.

5. The method of claim 1, wherein the digital code is a modulator bitstream, and wherein the method further comprises converting the modulator bitstream into a multi-bit value.

6. The method of claim 1, wherein the switching capacitor provides a charge current to a modulator capacitor.

7. The method of claim 1, wherein the switching capacitor is a switching capacitor equivalent resistor that provides charge current to a modulator capacitor of the sigma-delta modulator.

8. The method of claim 1, wherein measuring the capacitance further comprises alternately coupling the switching capacitor and a discharge resistor to a first node of a modulator capacitor of the sigma-delta modulator.

9. The method of claim 1, wherein measuring the capacitance further comprises:

charging a modulator capacitor of the sigma-delta modulator using a first charge on the switching capacitor to increase a voltage on the modulator capacitor;

when the voltage is equal to a reference voltage, discharging the modulator until the voltage is equal to the reference voltage; and

charging the modulator capacitor using a second charge on the switching capacitor to increase the voltage on the modulator capacitor.

10. The method of claim 1, wherein measuring the capacitance further comprises:

switching a switching capacitor between a voltage source and a first node of the modulator to provide a charge current to the modulator capacitor; and

discharging the voltage on the modulator capacitor when the voltage on the modulator capacitor reaches a reference voltage.

11. The method of claim 10, wherein discharging the voltage on the modulator capacitor comprises connecting a discharge resistor between the node of the modulator capacitor and ground using a switch controlled by an output signal of a comparator, wherein the comparator toggles the output signal when the voltage on the modulator capacitor crosses the reference voltage.

12. The method of claim 11, wherein the comparator is configured to toggle the switch when the voltage crosses the reference voltage in either a positive or negative direction.

13. The method of claim 10, wherein the switching capacitor, a first switch, and a second switch form a switching capacitor equivalent resistor to provide the charge current to the modulator capacitor.

14. The method of claim 10, wherein switching the switching capacitor further comprises switching a first switch and a second switch, wherein the first switch is coupled between the voltage source and a first node of the switching capacitor, and wherein the second switch is coupled between the first node of the switching capacitor and the first node of the modulator capacitor.

16. The apparatus of claim 14, wherein an output of the sigma-delta modulator is configured to switch the switching capacitor in the feedback loop of the sigma-delta modulator.

17. The apparatus of claim 14, wherein one end of the switching capacitor is coupled to a line, wherein the sigma-delta modulator is configured to measure the capacitance on the line, and wherein the switching capacitor is charged on the line.

18. The apparatus of claim 14, wherein the digital code is proportional to the measured capacitance.

19. The apparatus of claim 14, further comprising one or more digital filters coupled to receive an output of the sigma-delta modulator, wherein the output of the sigma-delta modulator is a digital output bitstream, and wherein the one or more digital filters are configured to convert the digital output bitstream into the digital code.

20. The apparatus of claim 19, wherein the digital output bitstream is a continuous, single-bit bitstream, and the converted digital code is a multi-bit value.

15. An apparatus, comprising:

a sensor element, wherein the sensor element is a switching capacitor; and

a sigma-delta modulator coupled to the sensor element to measure a capacitance on the sensor element and to convert the measured capacitance to a digital code wherein the switching capacitor is in a feedback loop of the sigma-delta modulator.

21. The apparatus of claim 15, wherein the sigma-delta modulator comprises a modulator capacitor, and wherein the switching capacitor is configured to provide a charge current to the modulator capacitor.

22. The apparatus of claim 15, wherein the switching capacitor is a switching capacitor equivalent resistor that provides charge current to a modulator capacitor of the sigma-delta modulator.

23. The apparatus of claim 21, wherein the sigma-delta modulator further comprises a discharge resistor to discharge the modulator capacitor.

24. The apparatus of claim 23, wherein the sigma-delta modulator further comprises a switch coupled to the discharge resistor and the output of the sigma-delta modulator, the output of the sigma-delta modulator to toggle the switch when a voltage on the modulator capacitor increases to be equal to a reference voltage and when the voltage on the modulator capacitor decreases to be equal to the reference voltage.

25. The apparatus of claim 23, wherein the sigma-delta modulator further comprises a switching circuit, wherein the switching circuit is configured to switch the switching capacitor between a voltage source and a first node of the modulator capacitor to provide a charge current to the modulator capacitor.

26. The apparatus of claim 25, wherein the switching circuit is further configured to alternately couple a discharge resistor to the first node of the modulator capacitor to discharge the voltage and the switching capacitor to the first node of the modulator capacitor to charge the voltage.

27. The apparatus of claim 25, wherein the switching circuit is configured to couple the switching capacitor in parallel to the modulator capacitor.

28. The apparatus of claim 23, wherein the sigma-delta modulator further comprises a switching circuit, wherein the switching circuit comprises a first switch coupled to a voltage source and a first node of the switching capacitor, and a second switch coupled to the first node of the switching capacitor and a first node of the modulator capacitor, wherein the switching capacitor, the first switch, and the second switch are configured to form a switching capacitor equivalent resistor to provide the charge current to the modulator capacitor.

29. The apparatus of claim 23, wherein the sigma-delta modulator further comprises a switching circuit coupled to the sensor element, wherein the switching circuit is configured to transfer charge on the sensor element, accumulated during a first phase, to the modulator capacitor during a second phase.

30. The apparatus of claim 29, wherein the switching circuit is further configured to couple a discharge resistor to discharge the transferred charge on the modulator capacitor.

31. The apparatus of claim 21, wherein the sigma-delta modulator further comprises a comparator, wherein the comparator is configured to toggle an output signal when the voltage on the modulator capacitor crosses the reference voltage.

32. The apparatus of claim 31, wherein the output signal of the comparator activates charging of the modulator capacitor when the voltage on the modulator capacitor is below the reference voltage, and activates discharging of the modulator capacitor when the voltage on the modulator capacitor is above the reference voltage.

33. The apparatus of claim 31, wherein the comparator is configured to toggle a switch, which couples and decouples a discharge resistor to a first node of the modulator capacitor.

34. The apparatus of claim 15, wherein the sigma-delta modulator comprises a linear transfer characteristic and a fixed measurement time.

35. The apparatus of claim 28, wherein the sigma-delta modulator further comprises:

a comparator configured to receive two inputs, wherein the two inputs are the voltage on the modulator capacitor and the reference voltage;

a latch coupled to an output of the comparator, wherein the latch is configured to latch the output of the comparator based on a clock signal; and

a gate coupled to receive an output of the latch and the clock signal, wherein the gate is configured to control the first and second switches of the switching circuit.

36. The apparatus of claim 35, wherein the discharge resistor is coupled between the voltage source and the first node of the modulator capacitor.

37. The apparatus of claim 28, wherein the sigma-delta modulator further comprises:

a comparator configured to receive two inputs, wherein the two inputs are the voltage on the modulator capacitor and the reference voltage;

a latch coupled to an output of the comparator, wherein the latch is configured to latch the output of the comparator based on a clock signal; and

a counter coupled to receive the clock signal, wherein the counter is configured to control the first and second switches of the switching circuit, wherein the switching circuit further comprises a third switch coupled the discharge resistor and ground, and wherein the output of the latch is configured to control the third switch.

38. The apparatus of claim 37, wherein the counter is a pseudo-random signal (PRS) counter, wherein the PRS is used as a spread spectrum source for electromagnetic interference (EMI) immunity.

39. The apparatus of claim 37, wherein the discharge resistor is coupled between the voltage source and the first node of the modulator capacitor, and wherein the third switch is coupled between the discharge resistor and the voltage source.

40. The apparatus of claim 28, further comprising:

a clock generation circuit coupled to the sigma-delta modulator, wherein the clock generation circuit is configured to provide a clock to the switching circuit; and

a digital filter coupled to the sigma-delta modulator, wherein the digital filter is configured to filter the output of the sigma-delta modulator.

41. The apparatus of claim 40, wherein the clock generation circuit and the output of the sigma-delta modulator set a sample frequency and an output bitstream frequency of the sigma-delta modulator.

42. The apparatus of claim 40, wherein the clock generation circuit comprises:

an oscillator to provide a clock signal to the sigma-delta modulator; and

a gate coupled to receive the clock signal and an output of the sigma-delta modulator, wherein an output signal of the gate is configured to control the switching circuit.

43. The apparatus of claim 40, wherein the clock generation comprises:

an oscillator to provide a clock signal to the sigma-delta modulator; and

a counter to receive the clock signal, wherein the counter is configured to control the switching circuit.

44. The apparatus of claim 40, wherein the clock generation circuit and the filter circuit comprise:

an oscillator to provide an oscillator signal;

a frequency divider coupled to receive the oscillator signal and to provide a clock signal to a latch of the sigma-delta modulator, wherein the latch is coupled to the output of a comparator of the sigma-delta modulator;

a pulse width modulator (PWM);

a gate coupled to receive an output of the latch and clock signal and an output of the PWM;

a first latch coupled to receive the clock signal, and wherein the first latch is enabled by the output of the gate, wherein an output of the first latch comprises the digital code; and

a second latch coupled to receive the oscillator signal, wherein the second latch is enabled by the output of the latch of the sigma-delta modulator, and wherein an output signal of the second latch is configured to control the switching circuit.

45. The apparatus of claim 44, wherein the clock generation circuit and digital filter circuit further comprises a pseudo-random signal (PRS) counter coupled between the oscillator and the second latch, wherein the PRS is used as a spread spectrum source for electromagnetic interference (EMI) immunity.

46. The apparatus of claim 40, wherein the clock generation circuit and digital filter circuit comprises:

an oscillator to provide an oscillator signal;

a frequency divider coupled to receive the oscillator signal and to provide a clock signal to a latch of the sigma-delta modulator, wherein the latch is coupled to the output of a comparator of the sigma-delta modulator, and wherein the frequency divider is configured to divide the oscillator signal by eight;

a first latch coupled to receive the oscillator signal, and wherein the first latch is enabled by the output of the latch of the sigma-delta modulator, wherein an output of the first latch is configured to control the switching circuit; and

a decimator coupled to receive the output of the latch of the sigma-delta modulator, and wherein an output of the decimator comprises the digital code.

47. The apparatus of claim 40, wherein the clock generation circuit and digital filter circuit comprises:

a modulator bitstream filter coupled to the sigma-delta modulator; and

a clock signal circuit coupled to the sigma-delta modulator to provide a clock signal to each of the switching circuit, the sigma-delta modulator, and the modulator bitstream filter.

48. The apparatus of claim 47, wherein the sigma-delta modulator comprises a comparator and a latch, wherein the comparator is configured to toggle an output signal when the voltage on the modulator capacitor crosses the reference voltage, wherein the latch is coupled to an output of the comparator and is configured to latch the output of the comparator based on the clock signal latch provided by the clock signal circuit, wherein the modulator bitstream filter comprises a pulse width modulator (PWM), a gate, and a counter, wherein the PWM is configured to receive the clock signal provided by the clock signal circuit, wherein the gate is configured to receive an output of the PWM and the output of the latch of the sigma-delta modulator, wherein the counter is configured to receive an output of the gate and the clock signal provided by the clock signal circuit, wherein an output of the counter comprises the digital code, and wherein the clock circuit comprises an IMO, and a VC, wherein the output of the VC is configured to provide the clock signals to the switching circuit, the PWM, and the counter.

49. The apparatus of claim 48, wherein the clock source circuit further comprises a clock source coupled to the IMO and the switching circuit, wherein the clock source is configured to provide the clock signal to the switching circuit.

50. The apparatus of claim 49, wherein the clock source is a 16-bit pseudo-random signal (PRS) counter.

51. The apparatus of claim 15, wherein the sigma-delta modulator is a capacitance-to-duty-cycle converter, wherein the modulator duty cycle of the sigma-delta modulator changes when a presence of a conductive object is detected on the sensor element.

52. The apparatus of claim 15, further comprising a decimator coupled to the sigma-delta modulator.

53. The apparatus of claim 15, further comprising a single layer, four wire Indium-tin-oxide (ITO) panel, wherein the single-layer, four wire ITO panel comprises the sensor element.

54. The apparatus of claim of claim 52, wherein the ITO panel comprises a solid ITO coating with the electric filed linearization electrodes.

55. The apparatus of claim of claim 52, wherein the ITO panel comprises multiple resistive sliders connected in parallel to provide linear electric field gradient over the ITO panel.

56. The apparatus of claim 15, further comprising a two-dimensional, four wire touch-sensor pad, wherein the two-dimensional, four wire touch-sensor pad wherein the single-layer, four wire ITO panel comprises the sensor element.

57. The apparatus of claim 15, further comprising a scanning matrix, wherein the scanning matrix comprises the sensor element.

58. The apparatus of claim 57, wherein the scanning matrix is implemented in a keyboard.

59. An apparatus, comprising:

means for measuring a capacitance on a sensor element; and

means for converting the capacitance measured on the sensor element to a digital code using a sigma-delta modulator.

60. The apparatus of claim 59, further comprising means for digital filtering an output of the sigma-delta modulator to generate a multi-bit value for the digital code.

61. The apparatus of claim 59, further comprising means for reducing a difference between the voltage of the modulator capacitor and the reference voltage.

62. The apparatus of claim 59, further comprising means for providing a continuous type operation for capacitance measurement on the sensor element.

63. The apparatus of claim 59, further comprising means for reducing a number of connection lines in a multi-button scanning application.

64. The apparatus of claim 63, wherein the multi-button scanning application is a keyboard.