TRANSMISSION LINE FILTER FOR ESD PROTECTION

• US 20080112101A1
• Filed: 11/14/2007
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Abandoned Application

• Current Assignee: SiBEAM, Inc. (Lattice Semiconductor Corporation)
• Original Assignee: SiBEAM, Inc. (Lattice Semiconductor Corporation)
• Inventors: McElwee, Patrick T., Gilbert, Jeffrey M., Doan, Chinh Huy
• Application Number:
  US11/939,726
• Publication Number:
  US 20080112101A1
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

An integrated circuit chip has on-chip millimeter wave (mmW) circuitry. An on-chip electro static discharge, ESD, protection network couples a signal pad of the chip to the mmW circuitry. The ESD protection network has a shorted stub being a low impedance path to ground for ESD events. Other embodiments are also described and claimed.

Claims

1. A circuit comprising:

a signal pad;

a shorted, shunt transmission line on-chip with the signal pad and having a near end coupled to the signal pad, and a far end coupled to power supply or ground, wherein frequency dependent absolute value of impedance looking into the near end is substantially less than the impedance seen looking into any other on-chip port that is coupled to the signal pad except for the port from which an ESD signal is introduced, over a frequency range that lies somewhere above dc and below 10 GHz.

2. The circuit of claim 1 wherein the near end is dc coupled to the signal pad.

3. The circuit of claim 2 wherein the far end is dc coupled to ground.

4. The circuit of claim 2 further comprising a capacitor having a near plate coupled to the near end, and a dc bias generator coupled to a far plate of the capacitor.

5. The circuit of claim 2 further comprising a capacitor having a near plate coupled to the far end and a far plate dc coupled to said ground or power supply.

6. The circuit of claim 5 further comprising:

a first diode coupling the far end to said power supply; and

a second diode coupling the far end to said ground.

7. The circuit of claim 6 further comprising a dc bias generator coupled to the far end.

8. An integrated circuit chip comprising:

a signal pad;

a first transmission line network having a first port and a second port, the first port being coupled to the signal pad;

a second transmission line network having a first port and a second port, its first port being coupled to the second port of the first transmission line network; and

a shorted stub having a near end and a far end, the near end being coupled between the second port of the first transmission line network and the first port of the second transmission line network,

wherein the shorted stub and the first and second transmission line networks are adapted to (1) implement a bandpass or highpass network to pass a desired signal that is somewhere in the range above 10 GHz between the signal pad and the second port of the second transmission line network, and (2) shunt to ground an undesired electro static discharge (ESD) signal that lies somewhere between DC and 10 GHz and that is received at the signal pad.

9. The integrated circuit chip of claim 8 wherein the shorted stub can shunt the undesired ESD signal in accordance with an electronics industry standard for ESD protection.

10. The integrated circuit chip of claim 8 wherein the second transmission line network comprises a series coupled capacitor between its first and second ports.

11. The integrated circuit of claim 10 further comprising a dc bias generator coupled to the second transmission line network at a point downstream of the capacitor.

12. The integrated circuit of claim 8 wherein the shorted stub has its far end dc coupled to said ground.

13. The integrated circuit of claim 8 wherein the shorted stub has its far end ac coupled to said ground via a capacitor that acts as essentially a short at some frequency above 10 GHz.

14. The integrated circuit of claim 13 further comprising:

a first diode coupling the far end of the shorted stub to a power supply node; and

a second diode coupling the far end of the shorted stub to said ground.

15. The integrated circuit of claim 14 further comprising a dc bias generator coupled to the far end of the shorted stub.

16. An integrated circuit chip comprising:

a signal pad;

a first transmission line network having a first port and a second port;

a second transmission line network having a first port and a second port, its first port being coupled to the second port of the first transmission line network; and

a shorted stub having a near end and a far end, the near end being coupled between the second port of the first transmission line network and the first port of the second transmission line network,

wherein a frequency dependent absolute value of impedance looking into the near end of the shorted stub is smaller than a frequency dependent absolute value of impedance looking into the first port of the second transmission line network over a frequency range that lies somewhere above DC and below 10 GHz.

17. The integrated circuit chip of claim 16 wherein a frequency dependent absolute value of impedance looking into the near end of the shorted stub is larger than a frequency dependent absolute value of impedance looking into the first port of the second transmission line network over a frequency range that lies somewhere above 10 GHz.

18. The integrated circuit chip of claim 16 wherein the frequency dependent absolute value of impedance looking into the shorted stub is smaller by at least a factor of ten.

19. An electronic system comprising:

a millimeter wave (mmW) beam forming antenna array having an integrated circuit chip as a component, the chip having a signal pad, on-chip mmW circuitry, and an on-chip electro static discharge, ESD, protection network coupling the signal pad to the mmW circuitry, the ESD protection network having a shorted stub being a low impedance path to ground for ESD events.

20. The electronic system of claim 19 wherein the ESD protection network further comprises:

a first transmission line network having a first port and a second port, the first port being coupled to the signal pad upstream of the second port; and

a second transmission line network having a first port and a second port, its first port being coupled to the second port of the first transmission line network upstream of its second port, wherein

the shorted stub has a near end and a far end, the near end being coupled between the second port of the first transmission line network and the first port of the second transmission line network, and a frequency dependent absolute value of impedance looking into the near end of the shorted stub is smaller than a frequency dependent absolute value of impedance looking into the first port of the second transmission line network over a frequency range that lies somewhere above DC and below 10 GHz.

21. The electronic system of claim 19 wherein a frequency dependent absolute value of impedance looking into the near end of the shorted stub is larger than a frequency dependent absolute value of impedance looking into the first port of the second transmission line network over a frequency range that lies somewhere above 10 GHz.

22. The electronic system of claim 19 wherein the integrated circuit chip has been manufactured by a CMOS process.

23. The electronic system of claim 19 in combination with a consumer product grade audio and/or video digital media receiver, wherein the antenna array is coupled to receive an audio and/or video stream from the media receiver and transmit the stream.

24. The electronic system of claim 19 in combination with a consumer product grade audio and/or video digital media player, wherein the antenna array is coupled to send a received audio and/or video stream to the media player for playback.