HYBRID FLASH MEMORY DEVICE AND METHOD FOR ASSIGNING RESERVED BLOCKS THEREOF

• US 20080112238A1
• Filed: 12/20/2006
• Published: 05/15/2008
• Est. Priority Date: 10/25/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Seon-Taek, Lee, Byoung-Kook
• Granted Patent: US 7,453,712 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area The device includes a hidden area including a first reserved block area and a second reserved block area, wherein the first reserved block area includes a plurality of first memory blocks having the same number of stored bits per cell as the first area, the second reserved block area includes a plurality of second memory blocks having the same number of stored bits per cell as the second area, and a flash translation layer configured to replace a bad block generated in the first main area with the first memory block and replace a bad block generated in the second main area with the second memory block, wherein the flash translation layer flexibly assigns functions of the first memory blocks or the second memory blocks depending on whether the first and second memory blocks are all used.

Claims

1. A hybrid flash memory device comprising:

an array including a first area and a second area having a larger number of stored bits per cell than the first area;

a hidden area including a first reserved block area and a second reserved block area, wherein the first reserved block area includes a plurality of first memory blocks having the same number of stored bits per cell as the first area, the second reserved block area includes a plurality of second memory blocks having the same number of stored bits per cell as the second area; and

a flash translation layer configured to replace a bad block generated in the first main area with the first memory block and replace a bad block generated in the second main area with the second memory block, wherein the flash translation layer flexibly assigns functions of the first and second memory blocks depending on whether the first memory blocks or the second memory blocks are all used.

2. The hybrid flash memory device as set forth in claim 1, wherein the flash translation layer is configured to replace the bad block generated in the first main area using the one or more second memory blocks when the first memory blocks are all used.

3. The hybrid flash memory device as set forth in claim 1, wherein the flash translation layer is configured to replace the bad block generated in the second main area using the two or more first memory blocks when the second memory blocks are all used.

4. The hybrid flash memory device as set forth in claim 1, wherein the boundary between the first and second reserved block areas is fixed.

5. The hybrid flash memory device as set forth in claim 1, wherein the boundary between the first and second reserved block areas is flexibly variable according to whether the first memory blocks or the second memory blocks are all used.

6. The hybrid flash memory device as set forth in claim 1, wherein the flash translation layer is configured to vary the boundary between the first and second reserved block areas to extend the first reserved block area when the first memory blocks are all used.

7. The hybrid flash memory device as set forth in claim 1, wherein the flash translation layer is configured to vary the boundary between the first and second reserved block areas to extend the second reserved block area when the second memory blocks are all used.

8. The hybrid flash memory device as set forth in claim 1, wherein the hidden area further includes a hidden information storage area in which memory block assignment information of the first and second reserved block areas is stored.

9. The hybrid flash memory device as set forth in claim 8, wherein a result of replacement for the bad block generated in the first or second main area is stored in the hidden information storage area.

10. The hybrid flash memory device as set forth in claim 1, being a one-NAND flash memory device.

11. A computer readable media embodying instructions executable by a processor to perform a method for assigning reserved blocks of a flash memory device, the method comprising:

setting a boundary of a first reserved block area for replacing bad blocks generated in a first block and a boundary of a second reserved block area for replacing bad blocks generated in a second area having a larger number of stored bits per cell than the first area; and

flexibly assigning functions of memory blocks of the first and second reserved block areas when memory blocks of the first reserved block or the second reserved block area are all used.

12. The method as recited in claim 11, wherein the boundary of the second reserved block area is set larger than that of the first reserved block area.

13. The method as recited in claim 11, further comprising replacing the bad block generated in the first area with at least one memory block included in the second reserved block area when memory blocks included in the first reserved block area are all used.

14. The method as recited in claim 11, further comprising replacing the bad block generated in the second area with at least two memory blocks included in the first reserved block area when memory blocks included in the second reserved block area are all used.

15. The method as recited in claim 11, wherein the boundary between the first and second reserved block areas is fixed.

16. The method as set forth in claim 11, wherein the boundary between the first and second reserved block areas is flexibly variable with whether the first memory blocks or the second memory blocks are all used.

17. The method as recited in claim 11, further comprising changing the boundary between the first and second reserved block areas to extend the first reserved block area when memory blocks of the first reserved block area are all used.

18. The method as recited in claim 11, further comprising changing the boundary between the first and second reserved block areas to extend the second reserved block area when memory blocks of the second reserved block area are all used.

19. The method as recited in claim 11, flexibly assigning functions of memory blocks further comprises:

storing area assignment information of the first and second reserved block areas in a hidden information storage area of a flash memory device.

20. The method as recited in claim 11, flexibly assigning functions of memory blocks further comprises:

storing a result of replacement for the bad block generated in the first or second main area in a hidden information storage area of a flash memory device.