SEMICONDUCTOR MEMORY DEVICES HAVING OPTIMIZED MEMORY BLOCK ORGANIZATION AND DATA LINE ROUTING FOR REDUCING CHIP SIZE AND INCREASING SPEED

• US 20080112251A1
• Filed: 11/06/2007
• Published: 05/15/2008
• Est. Priority Date: 11/10/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rehh, Sang-Jae, Youn, Jae-Youn
• Granted Patent: US 7,738,311 B2
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.

Claims

1. A semiconductor memory device, comprising:

a memory array comprising a plurality of memory banks, wherein each bank is divided into a plurality of sub-banks;

a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level;

a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and

a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines.

2. The semiconductor memory device of claim 1, wherein the groups of data I/O lines are connected to I/O sense amplifiers disposed in regions of the memory array between adjacent banks.

3. The semiconductor memory device of claim 1, wherein the memory device comprises a DRAM with edge pad topology.

4. The semiconductor memory device of claim 1, wherein each subbank of a given memory Bank is arranged along a row in the first direction.

5. The semiconductor memory device of claim 4, wherein at least two banks have rows of subbanks that are adjacent to each other with word line decode circuitry interposed there between.

6. The semiconductor memory device of claim 5, wherein at least two subbanks of a given bank share a same column decoder for the bank.

7. The semiconductor memory device of claim 1, wherein the third set of data I/O lines are connected to I/O circuitry disposed in a central region between adjacent pairs of memory banks.

8. The semiconductor memory device of claim 7, further comprising a fourth set of data I/O lines connected to the I/O circuitry and extending in the first direction between the central region across one or more sub-banks toward a peripheral edge region and connected to I/O pads disposed on the peripheral edge region.

9. The semiconductor memory device of claim 8, wherein the fourth set of data I/O lines are formed in the third metallization level.

10. A multi-bank integrated circuit memory device comprising a plurality of independently controlled memory banks, wherein each memory bank is divided into a plurality of sub-banks arranged in a plurality of rows and columns of sub-banks of memory cells, wherein the sub-banks of each bank being located along the same row of sub-banks of memory cells.

11. The multi-bank integrated circuit memory device of claim 10, wherein each column of subbanks of memory cells includes one subbank of each memory bank.

12. The multi-bank integrated circuit memory device of claim 11, wherein each column of subbanks of memory cells includes one subbank of each memory bank which commonly share I/O sense amplifier circuitry.

13. The multi-bank integrated circuit memory device of claim 10, wherein each bank has separate column decode circuit blocks that control different subbanks for the bank.

14. The multi-bank integrated circuit memory device of claim 10, wherein at least two banks have rows of subbanks that are adjacent to each other with word line decode circuitry interposed there between.

15. The multi-bank integrated circuit memory device of claim 10 further comprising:

a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level;

a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and

a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines.

16. The multi-bank integrated circuit memory device of claim 15, wherein the third set of data I/O lines are connected to I/O circuitry disposed in a central region between adjacent pairs of memory banks.

17. The multi-bank integrated circuit memory device of claim 16 further comprising a fourth set of data I/O lines connected to the I/O circuitry and extending in the first direction between the central region across one or more sub-banks toward a peripheral edge region and connected to I/O pads disposed on the peripheral edge region.

18. The multi-bank integrated circuit memory device of claim 17 wherein the fourth set of data I/O lines are formed in the third metallization level.