APPARATUS FOR CONTROLLING GIO LINE AND CONTROL METHOD THEREOF

• US 20080112252A1
• Filed: 05/30/2007
• Published: 05/15/2008
• Est. Priority Date: 11/14/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Jee Yul
• Granted Patent: US 7,668,036 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A control apparatus of a GIO line includes a plurality of GIO line termination units, and a GIO control unit for generating a control signal to activate an operation of a specific one of the plurality of GIO termination units according to a data transmission method. Further, a method of controlling a GIO line through GIO termination includes the step of generating a control signal to activate an operation of a specific one of a plurality of GIO termination units according to a data transmission method.

Claims

1. A control apparatus of a GIO line, comprising:

a plurality of Global Input Output (GIO) line termination units, and

a GIO control unit for generating a control signal to activate an operation of a specific one of the plurality of GIO termination units according to a data transmission method.

2. The control apparatus of claim 1, wherein the termination unit raises or lowers a voltage level of the GIO line to a specific level before data is driven to the GIO line.

3. The control apparatus of claim 1, further comprising a row address processing unit for controlling an output of a block address signal with respect to a specific one of a plurality of banks according to a CAS command signal, and outputs the row address signal.

4. The control apparatus of claim 1, wherein the GIO control unit generates a control signal to activate an operation of a specific one of the plurality of GIO termination units in response a column address signal, a row address signal and a data transmission method select signal.

5. The control apparatus of claim 3, wherein the row address processing unit comprises:

a plurality of address signal storage units including a transfer gate for transferring the block address signal in response to the CAS command signal; and

a latch unit for temporarily storing an output of the address signal storage unit.

6. The control apparatus of claim 4, wherein the data transmission method select signal decides a data transmission method in any one of X4, X8 and X16 forms.

7. The control apparatus of claim 6, wherein the GIO control unit generates a control signal to activate an operation of one of the plurality of GIO termination units when the data transmission method select signal is a signal to decide the data transmission method in X4 form.

8. The control apparatus of claim 6, wherein the GIO control unit generates a control signal to activate an operation of two of the plurality of GIO termination units when the data transmission method select signal is a signal to decide the data transmission method in X8 form.

9. The control apparatus of claim 1, wherein the GIO control unit comprises:

a GIO termination unit for outputting a signal to determine whether to terminate a specific GIO line group in response to the column address signal, a row address signal and a data transmission method select signal, and

a pulse width control unit for controlling a pulse width of an output signal of the GIO termination unit.

10. The control apparatus of claim 9, wherein the GIO termination select unit comprises:

a first NAND gate for receiving a signal, which is obtained by performing a NOR operation on the column address signal and a specific data transmission method select signal, as an input;

a second NAND gate for receiving the row address signal and an inverted signal of the specific data transmission method select signal as inputs;

a third NAND gate for receiving a signal, which is obtained by performing a NAND operation on an output signal of the first NAND gate and the specific data transmission method select signal, as an input; and

a fourth NAND gate for receiving an output signal of the second NAND gate and an inverted signal of the specific data transmission method select signal.

11. The control apparatus of claim 10, wherein the GIO termination select unit comprises:

a fifth NAND gate for receiving an output signal of the first NAND gate and an output signal of the second NAND gate as inputs;

a sixth NAND gate for receiving an output signal of the second NAND gate and an output signal of the third NAND gate as inputs;

a seventh NAND gate for receiving an output signal of the first NAND gate and an output signal of the fourth NAND gate as inputs;

an eighth NAND gate for receiving an output signal of the third NAND gate and an output signal of the fourth NAND gate as inputs; and

first to fourth inverters for inverting outputs of the fifth to eighth NAND gates, respectively, and outputting inverted signals.

12. The control apparatus of claim 9, wherein the pulse width control unit comprises:

a normalization unit for normalizing a pulse width of an output signal of the GIO termination select unit; and

a signal extension unit for extending an output signal of the normalization unit for a specific period of time.

13. The control apparatus of claim 12, wherein the normalization unit normalizes a pulse width of the output signal of the GIO termination select unit to a pulse width of the pulse signal in response to an output signal of the GIO termination select unit and a pulse signal having a pulse width.

14. The control apparatus of claim 12, wherein the normalization unit comprises:

a plurality of NAND gates for receiving output signals of the GIO termination select units, respectively, and a pulse signal having a pulse width as inputs; and

a plurality of inverters for inverting output signals of the NAND gates, respectively.

15. The control apparatus of claim 12, wherein the signal extension unit comprises:

a plurality of inverters for inverting output signals of the normalization units, respectively;

a plurality of delay units for delaying output signals of the inverters, respectively, for a specific period of time; and

a plurality of NAND gates for receiving output signals of the inverters and output signals of the delay units, respectively, as inputs.

16. A method of controlling a GIO line through GIO termination, comprising the step of:

generating a control signal to activate an operation of a specific one of a plurality of GIO termination units according to a data transmission method.

17. The control method of claim 16, further comprising the step of controlling an output of a block address signal with respect to a specific one of a plurality of banks according to a CAS command signal, and outputting a row address signal.

18. The control method of claim 16, wherein the step of generating the control signal includes receiving a column address signal, a row address signal and a data transmission method select signal, and generating a control signal to activate an operation of a specific one of a plurality of GIO termination units.

19. The control method of claim 17, wherein the step of outputting the row address signal comprises:

a step of outputting the block address signals through a plurality of transfer gates controlled in response to a CAS command signal on a bank basis; and

a latch step of temporarily storing the output block address signal.

20. The control method of claim 18, wherein the data transmission method select signal decides a data transmission method in any one of X4, X8 and X16 forms.

21. The control method of claim 18, wherein the step of generating the control signal includes generating a control signal to activate an operation of one of the plurality of GIO termination units when the data transmission method select signal is a signal to decide the data transmission method in X4 form.

22. The control method of claim 18, wherein the step of generating the control signal includes generating a control signal to activate an operation of two of the plurality of GIO termination units when the data transmission method select signal is a signal to decide the data transmission method in X8 form.

23. The control method of claim 16, wherein the step of generating the control signal comprises:

a step of receiving the column address signal, a row address signal and a data transmission method select signal, and outputting a signal to determine whether to terminate a specific GIO line group, and

a pulse width control step of controlling a pulse width of a signal to determine the termination.

24. The control method of claim 23, wherein the step of outputting a signal to determine the termination comprises:

a first NAND step of performing a NAND operation on a signal in which a NOR operation has performed on the column address signal and a specific data transmission method select signal;

a second NAND step of performing a NAND operation on the row address signal and an inverted signal of a specific data transmission method select signal;

a third NAND step of performing a NAND operation on an output signal of the first NAND step and the specific data transmission method select signal; and

a fourth NAND step of performing a NAND operation on an output signal of the second NAND step and an inverted signal of the specific data transmission method select signal.

25. The control method of claim 24, wherein the step of outputting a signal to determine the termination comprises:

a fifth NAND step of performing a NAND operation on an output signal of the first NAND step and an output signal of the second NAND step;

a sixth NAND step of performing a NAND operation on an output signal of the second NAND step and an output signal of the third NAND step;

a seventh NAND step of performing a NAND operation on an output signal of the first NAND step and an output signal of the fourth NAND step;

an eighth NAND step of performing a NAND operation on an output signal of the third NAND step and an output signal of the fourth NAND step; and

first to fourth inverters for inverting output signals of the fifth to eighth NAND steps, respectively, and outputting inverted signals.

26. The control method of claim 23, wherein the pulse width control step comprises:

a step of normalizing a pulse width of a signal to determine the termination; and

a signal extension step of extending an output signal of the normalization step for a specific period of time.

27. The control method of claim 26, wherein the normalization step includes normalizing a pulse width of a signal to determine the termination to a pulse width of the pulse signal in response to the signal to determine the termination, and a pulse signal having a pulse width.

28. The control method of claim 26 wherein the normalization step comprises the steps of:

performing a NAND operation on an output signal of each of the steps of outputting the signal to determining the termination, and a pulse signal having a pulse width; and

inverting output signals of the NAND operation steps, respectively.

29. The control method of claim 26, wherein the signal extension step comprises:

a step of delaying the inverted signals for a specific period of time; and

a NAND operation step of performing a NAND operation on the inverted signal and the signal delayed for a specific period of time.