LOW FABRICATION COST, HIGH PERFORMANCE, HIGH RELIABILITY CHIP SCALE PACKAGE

• US 20080113504A1
• Filed: 10/31/2007
• Published: 05/15/2008
• Est. Priority Date: 05/01/2002
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lee, Jin-Yuan, Huang, Ching-Cheng, Lin, Chuen-Jye
• Application Number:
  US11/930,224
• Publication Number:
  US 20080113504A1
• Time in Patent Office: Days
• US Class Current: 438/614
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/15 Structure, shape, material or disposition of the bump connectors after the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H04B 1/7113 : Determination of path profile
• CPC Class Codes: H04B 1/712 : Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Claims

1. A method for fabricating a metal bump over a first device, wherein said first device comprises a silicon substrate, a copper pad over said silicon substrate, a passivation layer over said silicon substrate, and a polymer layer on said passivation layer, wherein an opening in said passivation layer and in said polymer layer exposes said copper pad, wherein said metal bump connects said first device to a second device, and wherein an underfill is between said first and second devices and encloses said metal bump, comprising:

forming a first metal layer over said copper pad and over said polymer layer;

forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;

forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;

removing said first photoresist layer;

forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;

electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a height between 10 and 100 micrometers;

removing said second photoresist layer; and

reducing a transverse dimension of said copper pillar to be smaller than said height of said copper pillar and removing said first metal layer not under said second metal layer, wherein said underfill encloses said copper pillar.

2. The method of claim 1, wherein said polymer layer comprises polyimide.

3. The method of claim 1, wherein said first metal layer comprises titanium.

4. The method of claim 1, wherein said first metal layer comprises tantalum.

5. The method of claim 1, wherein said first metal layer comprises copper.

6. The method of claim 1, wherein said forming said first metal layer comprises a sputtering process.

7. The method of claim 1, wherein said forming said second metal layer comprises an electroplating process.

8. A method for fabricating a metal bump over a first device, wherein said first device comprises a silicon substrate, a copper pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said copper pad, wherein said metal bump connects said first device to a second device, and wherein an underfill is between said first and second devices and encloses said metal bump, comprising:

providing a silicon substrate, a copper pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said copper pad;

forming a first metal layer over said copper pad and over said passivation layer;

forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;

forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;

removing said first photoresist layer;

forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;

electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a height between 10 and 100 micrometers;

removing said second photoresist layer; and

reducing a transverse dimension of said copper pillar to be smaller than said height of said copper pillar and removing said first metal layer not under said second metal layer, wherein said underfill encloses said copper pillar.

9. The method of claim 8, wherein said first metal layer comprises titanium.

10. The method of claim 8, wherein said first metal layer comprises tantalum.

11. The method of claim 8, wherein said first metal layer comprises copper.

12. The method of claim 8, wherein said forming said first metal layer comprises a sputtering process.

13. The method of claim 8, wherein said forming said second metal layer comprises an electroplating process.

14. A method for fabricating a metal bump over a device, comprising:

providing a silicon substrate, a copper pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said copper pad;

forming a first metal layer over said copper pad and over said passivation layer;

forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;

forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;

removing said first photoresist layer;

forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;

electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a thickness between 10 and 100 micrometers;

electroplating a solder layer over said copper pillar in said opening in said second photoresist layer, wherein said solder layer has a height between 10 and 100 micrometers;

removing said second photoresist layer; and

reducing a transverse dimension of said copper pillar to be smaller than said height of said copper pillar and removing said first metal layer not under said second metal layer.

16. The method of claim 16, wherein said first metal layer comprises titanium.

15. The method of claim 16, wherein said first metal layer has a thickness of between 100 and 1,000 Angstroms.

17. The method of claim 16, wherein said first metal layer comprises tantalum.

18. The method of claim 16, wherein said first metal layer comprises copper.

19. The method of claim 16, wherein said forming said first metal layer comprises a sputtering process.

20. The method of claim 16, wherein said forming said second metal layer comprises an electroplating process.