METHOD OF FORMING A THROUGH-SUBSTRATE VIA

• US 20080113505A1
• Filed: 11/13/2006
• Published: 05/15/2008
• Est. Priority Date: 11/13/2006
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sparks, Terry G., Rauf, Shahid, Chatterjee, Ritwik, Alam, Syed M.
• Application Number:
  US11/558,988
• Publication Number:
  US 20080113505A1
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The hole is lined with a conductive layer. A dielectric layer is deposited over the conductive layer. This deposition is performed in a manner that causes the dielectric layer to be substantially conformal. Conductive material is formed over first dielectric layer. A second major surface of the substrate is etched to expose the conductive material.

Claims

1. A method, comprising:

providing a substrate having active circuitry on a first major surface;

forming a hole in the substrate through the first major surface;

lining the hole with a conductive layer;

depositing a first dielectric layer over the conductive layer in a manner that is substantially conformal;

forming a conductive material over the first dielectric layer; and

etching a second major surface of the substrate to expose the conductive material.

2. The method of claim 1, further comprising depositing a second dielectric layer in the hole in a manner that is substantially conformal prior to the step of lining the hole with the conductive layer.

3. The method of claim 2, further comprising forming a first barrier layer over the first dielectric layer prior to the step of forming the first conductive layer.

4. The method of claim 3, further comprising forming a second barrier layer over the second dielectric layer in a manner that is substantially conformal prior to the step of lining the hole with the conductive layer.

5. The method of claim 3, wherein the steps of forming the first and second barrier layers are further characterized by the first and second barrier layers comprising a metal.

6. The method of claim 1, further comprising forming a seed layer over the first dielectric layer prior to the step of forming the conductive layer, wherein the step of forming the conductive material comprises plating.

7. The method of claim 6, wherein the step of forming the conductive material is further characterized as filling the hole with the conductive material.

8. The method of claim 7, wherein the step of forming the conductive material is further characterized by the conductive material comprising copper.

9. The method of claim 1, further comprising:

performing chemical mechanical polishing to form a substantially planar surface above the hole that is substantially coplanar with a top surface of a dielectric, wherein the dielectric is formed over the active circuitry.

10. The method of claim 9, further comprising:

forming an interconnect over the active circuitry having a first conductive line and a second conductive line after the step of performing chemical mechanical polishing;

forming a first via between the first conductive line and the active circuitry;

forming a second via between the second conductive line and the active circuitry;

forming a third via between the first conductive line and the conductive layer; and

forming a fourth via between the second conductive line and the conductive material.

11. The method of claim 10, wherein the step of forming the interconnect is further characterized by the first conductive line being a ground line and the second conductive line being a signal line.

12. The method of claim 10, wherein the step of forming the interconnect is further characterized by the first conductive line being a first power supply line and the second conductive line being a second power supply line.

13. The method of claim 12, wherein the step of forming the interconnect is further characterized by the first power supply line being a positive power supply line and the second power supply line being a ground line.

14. The method of claim 1, further comprising forming a dielectric layer over the active circuitry.

15. A method of forming a through-substrate via, comprising:

providing a substrate having a first major surface;

forming a hole in the substrate through the first major surface;

depositing a substantially conformal conductive layer in the hole;

depositing a substantially conformal first dielectric layer over the conductive layer;

forming a conductive material over the substantially conformal first dielectric layer;

etching a second major surface of the substrate to expose the conductive material and the substantially conformal conductive layer; and

performing chemical mechanical polishing on the first major surface to expose the conductive material and the substantially conformal conductive layer.

16. The method of claim 15, further comprising:

providing active circuitry over the first major surface;

forming an interconnect over the active circuitry having a first conductive line and a second conductive line after the step of performing chemical mechanical polishing;

forming a first via between the first conductive line and the active circuitry;

forming a second via between the second conductive line and the active circuitry;

forming a third via between the first conductive line and the substantially conformal conductive layer; and

forming a fourth via between the first conductive line and the conductive material.

17. The method of claim 15, wherein the step of forming the interconnect is further characterized by the first conductive line being a ground line and the second conductive line being a signal line.

18. The method of claim 15, wherein the step of forming the interconnect is further characterized by the first conductive line being a positive power supply line and the second conductive line being a ground line.

19. The method of claim 15, further comprising:

depositing a substantially conformal second dielectric layer prior to the step of depositing the substantially conformal conductive layer;

depositing a substantially conformal first barrier layer over the first dielectric layer; and

forming a substantially conformal second barrier layer over the second dielectric layer;

wherein the step of etching comprises grinding; and

wherein the steps of forming the first and second barrier layers are further characterized by the first and second barrier layers comprising a metal.

20. A method, comprising:

providing substrate;

forming a hole in substrate;

forming a substantially conformal first metal layer in the hole;

forming a substantially conformal dielectric layer over the substantially conformal first metal layer;

forming a seed layer over the substantially conformal dielectric layer;

forming a second metal layer by plating on the seed layer; and

removing a portion of the substrate from a major surface sufficiently to expose the substantially conformal first metal layer and the second metal layer.