Augmenting semiconductor's devices quality and reliability

• US 20080114558A1
• Filed: 01/15/2008
• Published: 05/15/2008
• Est. Priority Date: 05/02/2005
• Status: Abandoned Application

• Current Assignee: Optimal Test Limited
• Original Assignee: Optimal Test Limited
• Inventors: Erez, Nir, Balog, Gil
• Application Number:
  US12/007,747
• Publication Number:
  US 20080114558A1
• Time in Patent Office: Days
• US Class Current: 702/81
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.

Claims

1. A method for augmenting quality or reliability of semiconductor units, comprising:

(a) providing at least two populations of semiconductor units that are subject to quality or reliability testing;

the populations include at least one quality or reliability fail candidate population and at least one other population;

(b) associating test flows to said populations;

each test flow includes stress testing sequence;

the stress testing sequence for at least one of said quality or reliability fail candidate populations includes a stress test of increased duration compared to duration of a stress test in the test flow of a population of at least one of said other populations;

the stress test sequence for at least one of said other populations includes a stress test operable under different temperature compared to corresponding operating temperature specification for a semiconductor unit of said semiconductor units;

(c) applying, within a sort testing stage, the corresponding test flow to each population and identifying any unit which failed the stress sequence.