Single Precision Vector Permute Immediate with "Word" Vector Write Mask

• US 20080114824A1
• Filed: 10/31/2006
• Published: 05/15/2008
• Est. Priority Date: 10/31/2006
• Status: Active Grant

• Current Assignee: Beijing Zitiao Network Technology Company Limited (ByteDance Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam James, Mejdrich, Eric Oliver
• Granted Patent: US 9,495,724 B2
• Time in Patent Office: Days
• US Class Current: 708/490
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06T 1/60 Memory management

Abstract

The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a cross product. The permute instructions may be dependent on one another and may require the use of temporary registers. Embodiments of the invention provide a permute instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby reducing the number of instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.

Claims

1. A method for storing data in a target register, comprising:

receiving a permute instruction specifying at least one source register, the target register, and a write mask, wherein the write mask identifies one or more locations of the target register for writing data; and

in response to receiving the permute instruction, transferring data from at least one location of the at least one source register to the one or more locations of the target register identified by the write mask.

2. The method of claim 1, wherein the write mask comprises a plurality of bits, wherein each bit is associated with a location of the target register.

3. The method of claim 2, wherein identifying the one or more locations of the target register comprises enabling one or more of the plurality of bits associated with the one or more locations of the target register.

4. The method of claim 3, wherein, enabling one or more of the plurality of bits associated with the one or more locations of the target register comprises setting the one or more bits to logic ‘

1’

.

5. The method of claim 1, wherein the one or more locations of the target register are word locations.

6. The method of claim 5, wherein each of the word locations comprise vector data.

7. A method for assembling data in a target register, comprising:

generating a plurality of permute instructions, each permute instruction specifying at least one source register and the target register;

setting a mask field in each of the plurality of permute instructions, wherein the mask field identifies one or more locations of the target register for receiving data from the source register; and

executing the permute instructions to assemble data from the source registers to the locations in the target register identified by the mask field.

8. The method of claim 7, wherein the mask field comprises a plurality of bits, wherein each bit is associated with a location of the target register.

9. The method of claim 8, wherein identifying the one or more locations of the target register comprises enabling one or more of the plurality of bits associated with the one or more locations of the target register.

10. The method of claim 9, wherein, enabling one or more of the plurality of bits associated with the one or more locations of the target register comprises setting the one or more bits to logic ‘

1’

.

11. The method of claim 7, wherein the one or more locations of the target register are word locations.

12. The method of claim 11, wherein each of the word locations comprise vector data.

14. The system of claim 12, wherein the write mask comprises a plurality of bits, wherein each bit is associated with a location of the target register.

15. The system of claim 14, one or more of the plurality of bits are enabled to identify the one or more locations of the target register.

16. The system of claim 15, to enable the one or more bits, the one or more bits are set to logic ‘

1’

.

17. The system of claim 12, wherein the one or more locations of the target register are word locations.

18. The system of claim 12, wherein each of the word locations comprise vector data.

13. A system, comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:

a register file comprising a plurality of registers; and

at least one vector unit, wherein the vector unit is configured to receive a permute instruction specifying at least one source register, a target register, and a write mask, the write mask identifying one or more locations in the target register, and execute the permute instruction by transferring data from at least one location of the at least one source register to the one or more locations of the target register identified by the write mask.