Single Precision Vector Dot Product with "Word" Vector Write Mask

• US 20080114826A1
• Filed: 10/31/2006
• Published: 05/15/2008
• Est. Priority Date: 10/31/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Muff, Adam James, Mejdrich, Eric Oliver
• Granted Patent: US 8,332,452 B2
• Time in Patent Office: Days
• US Class Current: 708/523
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78

Abstract

The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of dot product operations to generate operands for generating operands for a new vector. The dot product operations may require the issue of a plurality of permute instructions to arrange the vector operands in desired locations of a target register. Embodiments of the invention provide a dot product instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby avoiding the need for permute instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.

Claims

1. A method for storing data in a target register, comprising:

receiving a dot product instruction specifying at least one source register comprising vector operands for performing a dot product operation, the target register, and a write mask, wherein the write mask identifies one or more locations of the target register for writing data; and

in response to receiving the dot product instruction, performing the dot product operation and storing a scalar result of the dot product operation to the one or more locations of the target register identified by the write mask.

2. The method of claim 1, wherein the write mask comprises a plurality of bits, wherein the plurality of bits determine a value of the write mask, the value being associated with the one or more locations of the target register.

3. The method of claim 2, wherein each of the plurality of bits is associated with a location in the target register.

4. The method of claim 2, wherein identifying the one or more locations of the target register comprises enabling one or more of the plurality of bits associated with the one or more locations of the target register.

5. The method of claim 4, wherein, enabling one or more of the plurality of bits associated with the one or more locations of the target register comprises setting the one or more bits to logic ‘

1’

.

6. The method of claim 1, wherein the one or more locations of the target register are word locations.

7. The method of claim 6, wherein each of the word locations comprise vector data.

8. A method for constructing a vector in a target register, comprising:

generating a plurality of dot product instructions, each dot product instruction specifying at least one source register comprising vector operands for performing a dot product operation, and the target register, wherein each dot product instruction generates a scalar result representing an operand of the vector;

setting a mask field in each of the plurality of dot product instructions, wherein the mask field identifies one or more locations of the target register for storing the scalar result of the dot product operation; and

executing the dot product instructions to store each operand of the vector at the one or more locations in the target register identified by the mask field to construct the vector in the target register.

9. The method of claim 8, wherein the mask field comprises a plurality of bits, wherein the plurality of bits determine a value of the write mask, the value being associated with the one or more locations of the target register.

10. The method of claim 9, wherein identifying the one or more locations of the target register comprises enabling one or more of the plurality of bits associated with the one or more locations of the target register.

11. The method of claim 10, wherein, enabling one or more of the plurality of bits associated with the one or more locations of the target register comprises setting the one or more bits to logic ‘

1’

.

12. The method of claim 8, wherein the one or more locations of the target register are word locations.

13. The method of claim 12, wherein each of the word locations comprise vector data.

14. A system, comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:

a register file comprising a plurality of registers; and

at least one vector unit, wherein the vector unit is configured to;

receive a dot product instruction specifying at least one source register comprising vector operands for performing a dot product operation, a target register, and a write mask, the write mask identifying one or more locations in the target register, and

execute the dot product instruction by performing the dot product operation and storing a scalar result of the dot product operation to the one or more locations of the target register identified by the write mask.

15. The system of claim 14, wherein the write mask comprises a plurality of bits, wherein the plurality of bits determine a value of the write mask, the value being associated with the one or more locations of the target register.

16. The system of claim 15, wherein each of the plurality of bits is associated with a location in the target register.

17. The system of claim 15, wherein one or more of the plurality of bits are enabled to identify the one or more locations of the target register.

18. The system of claim 17, wherein to enable the one or more bits, the one or more bits are set to logic ‘

1’

.

19. The system of claim 14, wherein the one or more locations of the target register are word locations.

20. The system of claim 14, wherein each of the word locations comprise vector data.