SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS

• US 20080114919A1
• Filed: 01/14/2008
• Published: 05/15/2008
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Borkar, Nitin, Hofsheier, Richard, Pierce, Paul, Dermer, Gregory, Cheng, Kai, Wang, Wen-Hann, Rankin, Linda
• Granted Patent: US 7,603,508 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Claims

1. Apparatus comprising:

an interconnect to communicatively couple at least one processor with at least one input/output device, the interconnect including

at least one bridge to send and receive transactions between at least one input/output device and at least one processor; and

at least one crossbar coupled to at least one bridge to route transactions.

2. The apparatus of claim 1, further comprising:

at least one additional bridge to send and receive transactions between at least one input/output device and at least one processor.

3. The apparatus of claim 2 wherein at least one bridge supports a point-to-point protocol.

4. The apparatus of claim 3 wherein at least one bridge is to manage a translation of the point-to-point protocol to a protocol of the interconnect.

5. The apparatus of claim 1, further comprising:

at least one additional crossbar coupled to at least one bridge to route transactions.

6. The apparatus of claim 1 wherein at least one crossbar switch comprises non-blocking switches having a plurality of ports.

7. The apparatus of claim 6 wherein at least one crossbar supports independent power/on and reset of the ports.

8. The apparatus of claim 1 wherein a clock for at least one crossbar has a source that is independent of a clock for at least one processor.

9. The apparatus of claim 1, comprising at least one processing module having at least one processor, a memory, and a memory controller.

10. The apparatus of claim 1, comprising at least one processing module having at least one processor and the interconnect.

11. The apparatus of claim 1, comprising at least one input/output module having at least one input/output device and the interconnect.

12. The apparatus of claim 1, wherein at least one bridge is to packetize transactions between at least one processor and at least one input/output device in a format that is compatible with the crossbar.

13. The apparatus of claim 1, further comprising a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge.

14. The apparatus of claim 1, further comprising at least one DMA engine coupled to the crossbar, the DMA engine to facilitate message-passing between at least one processor and at least one additional processor.

15. A system, comprising:

at least one processor;

at least one input/output device; and

at least one interconnect including

at least one bridge to send and receive transactions between at least one input/output device and at least one processor; and

at least one crossbar coupled to at least one bridge to route transactions.

16. The system of claim 15 wherein the at least one interconnect is to support a communications protocol between at least one processor and at least one input/output device.

17. The system of claim 15 wherein the at least one interconnect may be separate from both the at least one processor and the at least one input/output device.

18. The system of claim 15, further comprising:

one or more buses to communicatively couple at least one processor and at least one input/output device;

19. The system of claim 15 wherein the interconnect manages a translation of a point-to-point protocol to a protocol of one or more buses.

20. The system of claim 15, comprising at least one processing module having at least one processor, a memory, and a memory controller.

21. The system of claim 20 wherein at least one additional interconnect is included in at least one of the processing modules.

22. The system of claim 15, further comprising:

at least one input/output module, wherein the at least one input/output module comprises at least one input/output device.

23. The system of claim 22 wherein at least one additional interconnect is included in at least one of the input/output modules.

24. An integrated circuit comprising:

a crossbar; and

a bridge communicatively coupled to the crossbar, the bridge to packetize transactions between at least one processor and at least one input/output device in a format that is compatible with the crossbar.

25. The integrated circuit of claim 24 further comprising a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge.

26. The integrated circuit of claim 25 further comprising:

at least one processing module, wherein the at least one processing module includes at least one processor, a memory, and a memory controller.

27. The integrated circuit of claim 26 further comprising:

at least one additional processing module comprising at least one additional processor, at least one additional memory, and at least one additional memory controller; and

at least one DMA engine coupled to the crossbar, the DMA engine to facilitate message-passing between the at least one processing module and the at least one additional processing module.

28. A method of operating an apparatus including at least one processor, at least one input/output device, and at least one interconnect component communicatively coupling at least one processor and at least one input/output device, the method comprising:

at least one interconnect component utilizing at least two bridges to send and receive transactions between at least one processor and at least one input/output device; and

at least one interconnect component utilizing at least two crossbar switches to route the transactions over a bus between at least two bridges.

29. The method of claim 28, further comprising:

at least one interconnect component utilizing at least two bridges to support a point-to-point protocol.

30. The method of claim 29, further comprising:

at least one interconnect component utilizing at least two bridges to manage a translation of the point-to-point protocol to a protocol of the interconnect component.