ELECTRONIC DEVICE WITH AN UPDATE AGENT THAT EMPLOYS PREPROCESSING TECHNIQUES FOR UPDATE

• US 20080114925A1
• Filed: 01/15/2008
• Published: 05/15/2008
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Yang, Xuguang
• Granted Patent: US 7,950,006 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

Methods of updating an electronic device having an update agent employing preprocessing techniques is disclosed. The methods described permit an electronic device having a non-volatile memory to update a plurality banks in an efficient manner, by preprocessing the original contents of the non-volatile memory. The preprocessing may comprise shifting one or more banks before performing an update, so as to create a moving, unoccupied bank or “bubble” into which the updated version of a bank may be stored. An embodiment of the present invention provides a reduction in the processing of the original memory contents, and extends the life of the non-volatile memory devices used.

Claims

1-31. -31. (canceled)

32. A computer-readable storage, having stored thereon a computer program having a plurality of code sections for updating an electronic device having a non-volatile memory comprising a reserved area and a plurality of banks containing a first code version from the first code version to a second code version according to a bank order having a penultimate bank, the code sections executable by a processor for causing the processor to perform the operations comprising:

moving the contents of the last bank in the bank order to the reserved area of the non-volatile memory;

shifting the contents of each bank in the bank order to the next bank in the bank order beginning with the penultimate bank in the bank order, and proceeding in descending bank order until the contents of the first bank in the bank order has been shifted to the second bank in the bank order;

converting the contents of each bank in the bank order from the first code version to the second code version in a fault tolerant manner beginning with the second bank in the bank order and proceeding in ascending bank order until the last bank in the bank order has been converted, each converted bank being stored in the previous bank in the bank order; and

transforming the contents of the reserved area from the first code version to the second code version in a fault tolerant manner, the second code version being stored in the bank that is last in the bank order.

33. The computer-readable storage of claim 32 wherein at least one of the moving and the shifting is performed coincident with at least one preprocessing technique.

34. The computer-readable storage of claim 33 wherein the at least one preprocessing technique comprises at least one of a bubbles technique, a nodes technique, and a shift region technique.

35. The computer-readable storage of claim 32 wherein the updating uses only two writes to each non-volatile memory location being updated.

36. The computer-readable storage of claim 32 wherein the code sections are executable by the processor to cause the processor to perform the operations comprising:

receiving an update package comprising at least one of at least a preprocessing instruction, an update instruction, and a bank order specification.

37. The computer-readable storage of claim 36 wherein the receiving uses a wireless network.

38. The computer-readable storage of claim 32 wherein at least one of the moving and shifting uses an offset of more than one bank.

39. The computer-readable storage of claim 32 wherein the electronic device comprises a mobile handset.

40. One or more circuits for use in an electronic device, the one or more circuits comprising:

a non-volatile memory comprising a reserved area and a plurality of banks containing a first code version; and

at least one processor communicatively coupled to the non-volatile memory, the at least one processor operating to, at least;

move the contents of a designated bank to the reserved area of the non-volatile memory, the designated bank thereby becoming an unoccupied bank;

shift the contents of each of the plurality of banks other than the designated bank from an original bank to an unoccupied bank in a bank by bank fashion, each original bank thereby temporarily becoming an unoccupied bank;

convert the contents of each of the plurality of banks other than the designated bank from the first code version to a second code version in a fault tolerant manner beginning with the contents of the last bank shifted and proceeding in reverse order of the shifting, the second code version of each bank being stored into the original bank from which the first code version of the bank was shifted; and

transform the contents of the reserved area of the non-volatile memory from the first code version to a second code version in a fault tolerant manner, the second code version being stored in the designated bank.

41. The one or more circuits of claim 40 wherein at least one of the moving, shifting, converting, and transforming is performed according to a specified bank order.

42. The one or more circuits of claim 40 wherein at least one of the moving and shifting further comprises preprocessing the contents of at least one of the plurality of banks.

43. The one or more circuits of claim 42 wherein the preprocessing comprises at least one of rearranging the contents of a bank, updating an address, updating a reference, and updating a branch instruction.

44. The one or more circuits of claim 42 wherein the preprocessing uses at least one of a bubbles technique, a nodes technique, and a shift regions technique.

45. The one or more circuits of claim 40 further comprising:

receiving an update package comprising at least one of a preprocessing instruction, an update instruction, and a bank order specification.

46. The one or more circuits of claim 45 wherein the receiving uses a public network.

47. The one or more circuits of claim 45 wherein the receiving uses a wireless network.

48. The one or more circuits of claim 40 wherein the updating of banks is performed according to a specified bank order.

49. The one or more circuits of claim 40 wherein the electronic device comprises a mobile handset.

50. An electronic device comprising non-volatile memory having a plurality of banks containing a first code version, the electronic device arranged to update the first code version by converting the first code version to a second code version in a fault tolerant manner, and wherein the updating requires only two writes to each memory location of each bank being updated.

51. The electronic device of claim 50 wherein the electronic device comprises a mobile handset.