METHOD AND SYSTEM FOR TRUSTED/UNTRUSTED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS

• US 20080115011A1
• Filed: 11/15/2006
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, William C., Chen, Xufeng, Codrescu, Lucian, Venkumahanti, Suresh, Pyla, Manojkumar, Giannini, Louis Achille
• Granted Patent: US 8,533,530 B2
• Time in Patent Office: Days
• US Class Current: 714/38
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

Claims

1. A method for determining and controlling trusted and untrusted debugging control of digital signal processor processes occurring in a digital signal processor, comprising:

determining an origin of debugging control as trusted debugging control or untrusted debugging control using a core processor process;

providing to the trusted debugging control a first set of features and privileges;

maintaining security in the operation of the core processor process according to a determination of the debugging control as untrusted debugging control or trusted debugging control.

2. The method of claim 1, further comprising providing the untrusted debugging control a second restricted set of features and privileges when the debugging control is untrusted debugging control.

3. The method of claim 1, further comprising providing read/write control for non-intrusive debugging configuration registers when the debugging control is trusted debugging control.

4. The method of claim 1, further comprising providing write control for debugging breakpoint configuration registers when the debugging control is trusted debugging control.

5. The method of claim 1, further comprising providing write control for debugging breakpoint address registers when the debugging control is trusted debugging control.

6. The method of claim 1, further comprising providing write control for instruction stuffing registers when the debugging control is trusted debugging control.

7. The method of claim 1, further comprising providing read/write control for a mailbox for debugging mechanism registers when the debugging control is either trusted debugging control or untrusted debugging control.

8. The method of claim 1, further comprising providing restricted write control for debugging command registers when the debugging control is untrusted debugging control.

9. The method of claim 1, further comprising providing read/write control for debugging mechanism general purpose registers when the debugging control is trusted debugging control.

10. The method of claim 1, further comprising providing read control for debugging mechanism enable registers when the debugging control is either trusted debugging control or untrusted debugging control.

11. The method of claim 1, further comprising determining whether debugging control is trusted debugging control or untrusted debugging control according to a value of a predetermined set of bits associated with a core processor system configuration register.

12. A digital signal processor debugging system for operation in association with a digital signal processor for determining and controlling trusted and untrusted debugging control of digital signal processor processes occurring in a digital signal processor, the system comprising:

a core processor control bit associated with a configuration register for determining the origin of debugging control as trusted debugging control or untrusted debugging control using a core processor process;

instructions associated with the core processor process and a debugging mechanism for providing to the trusted debugging control a first set of features and privileges when the debugging control is the trusted debugging control; and

means for maintaining security in the core processor process according to a determination of the debugging control as the untrusted debugging control or the untrusted debugging control.

13. The digital signal processor debugging system of claim 12, further comprising instructions associated with the core processor process and the debugging mechanism for providing the untrusted debugging control a second restricted set of features and privileges when the debugging control is untrusted debugging control.

14. The digital signal processor debugging system of claim 12, further comprising circuitry and instructions for providing read/write control for non-intrusive debugging configuration registers when the debugging control is the trusted debugging control.

15. The digital signal processor debugging system of claim 12, further comprising circuitry and instructions for providing write control for debugging breakpoint configuration registers when the debugging control is the trusted debugging control.

16. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing write control for debugging breakpoint address registers when the debugging control is trusted debugging control.

17. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing write control for instruction stuffing registers when the debugging control is trusted debugging control.

18. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing read/write control for mailbox to debugging mechanism registers when the debugging control is either the trusted debugging control or the untrusted debugging control.

19. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing restricted write control for debugging command registers when the debugging control is the untrusted debugging control.

20. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing read/write control for debugging mechanism general purpose registers when debugging control is the trusted debugging control.

21. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for providing read control for debugging mechanism enable registers when the debugging control is either the trusted debugging control or the untrusted debugging control.

22. The digital signal processor debugging system of claim 13, further comprising circuitry and instructions for determining whether debugging control is the trusted debugging control or the untrusted debugging control according to the value of a predetermined set of bits associated with a core processor system configuration register.

23. A digital signal processor for operation in support of a personal electronics device, the digital signal processor comprising means for maintaining security of digital signal processor processes during debugging operations of the digital signal processor, the digital signal processor comprising:

means for determining an origin of debugging control as trusted debugging control or untrusted debugging control using a core processor process;

means for providing to the trusted debugging control a first set of features and privileges when the debugging control is the trusted debugging control; and

means for maintaining security during operation of the core processor process according to a determination of the debugging control as the untrusted debugging control or the trusted debugging control.

24. The digital signal processor of claim 23, further comprising means for providing the untrusted debugging control a second restricted set of features and privileges when the debugging control is the untrusted debugging control.

25. The digital signal processor of claim 23, further comprising means for providing read/write control for non-intrusive debugging configuration registers when the debugging control is the trusted debugging control.

26. The digital signal processor of claim 23, further comprising means for providing write control for debugging breakpoint configuration registers when the debugging control is the trusted debugging control.

27. The digital signal processor of claim 23, further comprising means for providing write control for debugging breakpoint address registers when the debugging control is the trusted debugging control.

28. The digital signal processor of claim 23, further comprising means for providing write control for instruction stuffing registers when the debugging control is the trusted debugging control.

29. The digital signal processor of claim 23, further comprising means for providing read/write control to a mailbox for debugging mechanism registers when the debugging control is either the trusted debugging control or the untrusted debugging control.

30. The digital signal processor of claim 23, further comprising means for providing restricted write control for debugging command registers when the debugging control is the untrusted debugging control.

31. The digital signal processor of claim 23, further comprising means for providing read/write control for debugging mechanism general purpose registers when the debugging control is the trusted debugging control.

32. The digital signal processor system of claim 23, further comprising means for providing read control for debugging mechanism enable registers when the debugging control is either the trusted debugging control or the untrusted debugging control.

33. The digital signal processor system of claim 23, further comprising means for determining whether debugging control is the trusted debugging control or the untrusted debugging control according to a value of a predetermined set of bits associated with a core processor system configuration register.

34. A computer usable medium having computer readable program code means embodied therein for processing instructions on the digital signal processor for debugging a multi-threaded digital signal processor, the computer usable medium comprising:

computer readable program code means for determining an origin of debugging control as trusted debugging control or untrusted debugging control using a core processor process;

computer readable program code means for providing to the trusted debugging control a first set of features and privileges when the debugging control is the trusted debugging control;

computer readable program code means for providing the untrusted debugging control a second restricted set of features and privileges when the debugging control is the untrusted debugging control; and

computer readable program code means for maintaining security in the operating of the core processor process according to the determination of the debugging control as the untrusted debugging control or the trusted debugging control.

35. The computer usable medium of claim 34, further comprising computer readable program code means for determining whether debugging control is the trusted debugging control or the untrusted debugging control according to a value of a predetermined set of bits associated with a core processor system configuration register.