METHOD AND SYSTEM FOR TEST VERIFICATION OF INTEGRATED CIRCUIT DESIGNS

• US 20080115028A1
• Filed: 10/23/2006
• Published: 05/15/2008
• Est. Priority Date: 10/23/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Zoch, Randolph Wayne, Homer, Johnny Thurman, Hurley, William Milton
• Application Number:
  US11/551,940
• Publication Number:
  US 20080115028A1
• Time in Patent Office: Days
• US Class Current: 714/741
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308

Abstract

A method and system for verifying the design of an integrated circuit including an analog portion and a digital portion are disclosed. As one example, a method for verifying the design of an integrated circuit is disclosed, which includes the steps of generating an analog stimulus, performing a simulation test of the analog portion of the integrated circuit using the analog stimulus as an input, collecting data at an output of the analog portion of the integrated circuit, generating a digital stimulus with the collected data, performing a simulation test of the digital portion of the integrated circuit using the digital stimulus as an input, validating data at an output of the digital portion of the integrated circuit, regression testing the digital portion of the integrated circuit using the digital stimulus as an input, and comparing a result of the regression testing step with a result of the validating data step.

Claims

1. A method for verifying the design of an integrated circuit including an analog portion and a digital portion, comprising the steps of:

generating an analog stimulus;

performing a simulation test of the analog portion of the integrated circuit using the analog stimulus as an input;

collecting data at an output of the analog portion of the integrated circuit;

generating a digital stimulus with the collected data;

performing a simulation test of the digital portion of the integrated circuit using the digital stimulus as an input;

validating data at an output of the digital portion of the integrated circuit;

regression testing the digital portion of the integrated circuit using the digital stimulus as an input; and

comparing a result of the regression testing step with a result of the validating data step.

2. The method of claim 1, wherein the integrated circuit comprises an RFIC.

3. The method of claim 1, wherein the step of generating a digital stimulus comprises digitizing the data at the output of the analog portion of the integrated circuit.

4. The method of claim 1, wherein the integrated circuit includes a receiver arranged in an RFIC.

5. The method of claim 1, wherein the validating data step further comprises a step of conditioning the data at the output of the digital portion of the integrated circuit.

6. The method of claim 1, further comprising the steps of:

determining if the result of the regression testing step is substantially equal to the result of the validating data step; and

if so, determining that the integrated circuit has passed the regression testing.

7. The method of claim 1, wherein the data at the output of the analog portion of the integrated circuit is digitized with an analog-to-digital converter.

8. The method of claim 1, wherein the comparing step comprises comparing a valid output data set with a regression testing output data set.

9. The method of claim 1, wherein the validating step comprises a step of outputting a golden reference.

10. The method of claim 1, wherein the simulation test of the analog portion comprises at least one of a Matlab simulation and a Simulink simulation.

20. The system of claim 1, wherein the integrated circuit comprises an analog portion and a digital portion of a receiver subsystem of a transceiver.

11. A method for verifying the design of a mixed signal Radio Frequency Integrated Circuit, comprising the steps of:

generating a first test data set;

simulating a plurality of analog components of the mixed signal Radio Frequency Integrated Circuit using the first test data set as an input;

responsive to the step of simulating the plurality of analog components, outputting a second test data set;

simulating a plurality of digital components of the mixed signal Radio Frequency Integrated Circuit using the second test data set as an input;

responsive to the step of simulating the plurality of digital components, outputting a third test data set;

validating the third test data set;

regression testing the plurality of digital components using the second test data set as an input;

responsive to the regression testing step, outputting a fourth test data set; and

comparing the fourth test data set with the third test data set.

12. The method of claim 11, wherein the first test data set comprises an analog stimulus data set.

13. The method of claim 11, wherein the second test data set comprises a digital stimulus data set associated with a result of the step of simulating the plurality of analog components.

14. The method of claim 11, wherein the comparing step comprises comparing a regression test output data set with a validated simulation test output data set.

15. The method of claim 11, further comprising the steps of:

determining if data included in the fourth test data set is substantially equal to data included in the second test data set; and

if so, determining that the design of the Radio Frequency Integrated Circuit has passed the regression testing.

16. A system for verifying the design of an integrated circuit, comprising:

an analog portion of the integrated circuit;

a digital portion of the integrated circuit coupled to the analog portion; and

a processor unit coupled to the analog portion and the digital portion, the processor unit operable to;

generate an analog stimulus;

perform a simulation test of the analog portion of the integrated circuit using the analog stimulus as an input;

collect data at an output of the analog portion of the integrated circuit;

generate a digital stimulus with the collected data;

perform a simulation test of the digital portion of the integrated circuit using the digital stimulus as an input;

validate data at an output of the digital portion of the integrated circuit;

regression test the digital portion of the integrated circuit using the digital stimulus as an input; and

compare a result of the regression testing operation with a result of the validating data operation.

17. The system of claim 16, wherein the integrated circuit comprises a mixed signal device.

18. The system of claim 16, wherein a simulation test operation of the processor Unit is performed with a computer model.

19. The system of claim 16, wherein the processor unit is further operable to:

determine if the result of the regression testing operation is substantially equal to the result of the validating data operation; and

if so, assume that the integrated circuit has passed the regression testing operation.