Destination indication to aid in posted write buffer loading

• US 20080115039A1
• Filed: 10/31/2006
• Published: 05/15/2008
• Est. Priority Date: 10/31/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S.
• Granted Patent: US 7,836,380 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to detect a destination indication associated with received write data. In some embodiments, the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication. Other embodiments are described and claimed.

Claims

1. A memory device comprising:

a posted write buffer, wherein the posted write buffer includes a first element and a second element; and

logic to detect a destination indication associated with received write data, wherein the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication.

2. The memory device of claim 1, wherein if the received write data is to be stored in first element, then corresponding error correction code (ECC) is stored in the second element.

3. The memory device of claim 1, wherein the first element of the posted write buffer is physically separate from the second element of the posted write buffer.

4. The memory device of claim 3, wherein the first element of the posted write buffer is located on a first side of the memory device and the second element of the posted write buffer is located on a second side of the memory device.

5. The memory device of claim 1, further comprising:

a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits.

6. The memory device of claim 5, wherein the memory core includes a split bank pair of memory banks having a first memory bank corresponding to the first portion and a second memory bank corresponding to the second portion.

7. The memory device of claim 6, wherein data bits are to be stored in the first memory bank and corresponding ECC bits are to be stored in the second memory bank.

8. The memory device of claim 6, wherein the memory device is capable of operating in a memory check mode and a non-error check mode.

9. The memory device of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device.

10. A method comprising:

generating a write frame to be written to a memory device;

computing a destination indicator associated with the write frame, wherein the destination indicator indicates an element of a posted write buffer to which the write frame is to be written; and

sending the write frame to the memory device, wherein the write frame includes the destination indicator.

11. The method of claim 10, wherein the write frame further includes one or more error correction code (ECC) bits.

12. The method of claim 11, wherein the posted write buffer includes a first element and a second element.

13. The method of claim 12, further comprising:

receiving the write frame at a memory device;

posting the one or more ECC bits to either the first element or the second element of the posted write buffer based, at least in part, on the destination indicator.

14. The method of claim 13, further comprising:

receiving another write frame at the memory device, wherein the other write frame includes one or more data bits; and

posting the one or more data bits to either the first element or the second element of the posted write buffer based, at least in part, on the destination indicator.

15. The method of claim 14, wherein the memory device includes a memory core having a first portion to store the one or more data bits and a second portion to store the one or more ECC bits.

16. The method of claim 15, wherein the memory core includes a split bank pair of memory banks having a first memory bank corresponding to the first portion and a second memory bank corresponding to the second portion.

17. The method of claim 16, wherein the memory device is capable of operating in an error check mode and a non-error check mode.

18. The method of claim 17, wherein the memory device comprises a dynamic random access memory (DRAM) device.

19. A system comprising:

a memory controller; and

a memory device coupled with the memory controller, the memory device including

a posted write buffer, wherein the posted write buffer includes a first element and a second element; and

logic to detect a destination indication associated with received write data, wherein the logic determines whether to store the received write data in the first element or the second element based, at least in part, on the destination indication.

20. The system of claim 19, wherein data is to be stored in the first element if the corresponding error correction code (ECC) is stored in the second element.

21. The system of claim 20, wherein the first element of the posted write buffer is physically separate from the second element of the posted write buffer.

22. The system of claim 19, wherein the memory controller includes logic to generate a destination indicator associated with the write data.

23. The system of claim 22, wherein the memory device includes a memory core having a first portion to store the one or more data bits and a second portion to store the one or more ECC bits.

24. The system of claim 23, wherein the memory core includes a split bank pair of memory banks having a first memory bank corresponding to the first portion and a second memory bank corresponding to the second portion.

25. The system of claim 24, wherein the memory device is capable of operating in an error check mode and a non-error check mode.