NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREAD DIGITAL SIGNAL PROCESSOR

• US 20080115113A1
• Filed: 11/15/2006
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Pyla, Manojkumar, Chen, Xufeng, Anderson, William C., Codrescu, Lucian, Venkumahanti, Suresh, Giannini, Louis Achille
• Granted Patent: US 8,370,806 B2
• Time in Patent Office: Days
• US Class Current: 717/127
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Claims

1. A non-intrusive method for debugging a multi-threaded digital signal processor, comprising:

executing a plurality of processing instructions in a multi-threaded process using at least one or more threads of the multi-threaded digital signal processor;

identifying one or more breakpoint instructions for generating at least one debugging event;

generating the at least one debugging event in response to executing at least one of the breakpoint instructions;

executing a plurality of debugging instructions in response to the at least one debugging event, the debugging instructions for non-intrusively debugging the executing of the plurality of the processing instructions in the multi-threaded digital signal processor by transitioning at least one or more threads of the multi-threaded digital signal processor into a debugging mode; and

generating at least one debugging return from the executing of the plurality of debugging instructions for reporting the executing of the plurality of debugging instructions.

2. The method of claim 1, wherein the at least one debugging event occurs in response to an internally generated instance within the multi-threaded digital signal processor.

3. The method of claim 1, wherein the at least one debugging event occurs in response to an externally generated instance within the multi-threaded digital signal processor.

4. The method of claim 1 wherein the at least one debugging event occurs in response to a program counter reaching a predetermined count within the multi-threaded digital signal processor.

5. The method of claim 1 wherein the at least one or more threads of the multi-threaded digital signal processor transition out of the debugging mode.

6. The method of claim 1, wherein at least one or more instruction stuffing instructions perform a predetermined debugging algorithm relating to the operation of the multi-threaded digital signal processor.

7. The method of claim 1, wherein the at least one or more debugging instructions in the multi-threaded digital signal processor uses a JTAG interface interface between the executing of the plurality of debugging instructions and the executing of the plurality of processing instructions.

8. A system for operation for non-intrusively debugging a multi-threaded digital singal processor, comprising:

one or more of threads of the multi-threaded digital signal processor for executing a plurality of processing instructions in a digital signal multi-threaded process;

a set of breakpoint instructions for generating at least one debugging event;

debugging event generating instructions for generating at least one debugging event in response to executing at least one of the breakpoint instructions;

one or more of the threads for executing the plurality of debugging instructions in response to the at least one debugging event, the plurality of debugging instructions for non-intrusively debugging the executing of the plurality of processing instruction in the multi-threaded digital signal processor by transitioning at least one or more threads of the multi-threaded digital signal processor into a debugging mode; and

debugging return instructions for generating at least one debugging return from the executing of the plurality of debugging instructions for reporting the executing of the plurality of debugging instructions in the at least one or more threads of the multi-threaded digital signal processor.

9. The system of claim 8, further comprising circuitry and instructions for the debugging event to occur in response to a program counter reaching a predetermined count within the multi-threaded digital signal processor.

10. The system of claim 8, further comprising circuitry and instructions for transitioning the at least one or more threads of the multi-threaded digital signal processor out of the debugging mode.

11. The system of claim 8, further comprises a set of instruction stuffing instructions for performing a predetermined debugging algorithm relating to the operation of the multi-threaded digital signal processor.

12. The system of claim 8, further comprising circuitry and instructions for non-intrusively debugging the multi-threaded digital signal processor using a JTAG interface.

13. A mutli-threaded digital signal processor for operation in support of a personal electronics device, comprising non-intrusive means for debugging during multi-threaded processing, the non-intrusive debugging means comprising:

means for executing a plurality of processing instructions in a multi-threaded process using at least one or more threads of the multi-threaded digital signal processor;

means for identifying one or more breakpoint instructions for generating at least one debugging event;

means for generating at least one debugging event in response to executing at least one of the breakpoint instructions;

means for executing the plurality of debugging instructions in response to the at least one debugging event, the debugging instructions for non-intrusively debugging the executing of the plurality of processing instruction in the multi-threaded digital signal processor by transitioning the at least one or more threads of the multi-threaded digital signal processor into a debugging mode; and

means for generating at least one debugging return from the executing of the plurality of debugging instructions for reporting the executing of the plurality of debugging instructions in the at least one or more threads of the multi-threaded digital signal processor.

14. The digital signal processor system of claim 13, further comprising means for the debugging event to occur in response to an internally generated instance within the multi-threaded digital signal processor.

15. The multi-threaded digital signal processor of claim 13, further comprising means for the debugging event to occur in response to an externally generated instance within the multi-threaded digital signal processor.

16. The multi-threaded digital signal processor of claim 13, further comprising means for the debugging event to occur in response to a program counter reaching a predetermined count within the multi-threaded digital signal processor.

17. The mutli-threaded digital signal processor of claim 13, further comprising means for transitioning the at least one or more threads of the multi-threaded digital signal processor out of the debugging mode.

18. The multi-threaded digital signal processor of claim 13, further comprising means for stuffing instructions for performing a predetermined debugging algorithm relating to operation of the multi-threaded digital signal processor.

19. The multi-threaded digital signal processor of claim 13, further comprising means for using a JTAG interface between the executing of the plurality of debugging instructions and the executing of the plurality of processing instructions.

20. A computer usable medium having computer readable program code means embodied therein for processing instructions on the multi-threaded digital signal processor for non-intrusively debugging a multi-threaded digital signal processor, the computer usable medium comprising:

computer readable program code means for executing a plurality of processing instructions in a multi-threaded process using at least one or more threads of the multi-threaded digital signal processor;

computer readable program code means for identifying one or more breakpoint instructions for generating at least one debugging event;

computer readable program code means for generating at least one debugging event in response to executing at least one of the breakpoint instructions;

computer readable program code means for executing the plurality of debugging instructions in response to the at least one debugging event, the debugging instructions for non-intrusively debugging the executing of the plurality of processing instruction in the multi-threaded digital signal processor by transitioning at least one or more threads of the multi-threaded digital signal processor into a debugging mode; and

computer readable program code means for generating at least one debugging return from the executing of the plurality of debugging instructions for reporting the executing of the plurality of debugging instructions in the at least one or more threads of the multi-threaded digital signal processor.

21. The computer usable medium of claim 20, further comprising computer readable program code means for executing the plurality of debugging instructions in response to the at least one debugging event, the debugging event occurring in response to an internally generated instance within the multi-threaded digital signal processor.