EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS

• US 20080115115A1
• Filed: 11/15/2006
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chen, Xufeng, Anderson, William C., Codrescu, Lucian, Venkumahanti, Suresh, Pyla, Manojkumar, Giannini, Louis Achille
• Granted Patent: US 8,341,604 B2
• Time in Patent Office: Days
• US Class Current: 717/128
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 9/323 for indirect branch instructions

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Claims

1. A method for improving software instruction debugging operations by capturing real-time information relating to software execution flow in a digital signal processor, comprising:

operating a non-intrusive debugging process within a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processor of the digital signal processor;

non-intrusively monitoring software execution in real time for predetermined aspects of software execution associated with a core processing process and occurring in real-time in the digital signal processor;

recording selectable aspects of the non-intrusively monitored software execution;

generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution; and

controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint.

2. The method of claim 1, further comprising generating at least one record in response to a predetermined set of profiling counts.

3. The method of claim 1, further comprising non-intrusively monitoring the software execution of a selectable number of threads of the digital signal processor.

4. The method of claim 1, further comprising generating in response to a program counter value a trigger for initiating the non-intrusive debugging process.

5. The method of claim 1, further comprising generating a trigger for initiating the non-intrusive debugging process in response to a load/store address used in the software execution.

6. The method of claim 1, further comprising generating a plurality of records in response to a sequence of events occurring in the software execution.

7. The method of claim 1, further comprising generating at least one record in response to an external event occurring in relation to the software execution.

8. The method of claim 1, further comprising programming operation of the non-intrusive monitoring and the recording using a JTAG interface.

9. The method of claim 1, further comprising generating a packet stream of records derived from the recording for transmitting to a recording medium.

10. The method of claim 1, further comprising generating a packet stream of records derived from the recording for transmitting to an embedded trace buffer recording medium.

11. A digital signal processor debugging system for operation in association with a digital signal processor and including the ability to capture real-time information relating to software execution flow in a processor, comprising:

a debugging mechanism of the digital signal processor, a debugging mechanism associated with a core processor and operating a non-intrusive debugging process;

an embedded trace macrocell for non-intrusively monitoring software execution in real time for predetermined aspects of software execution associated with the core processing process;

recording instructions and associated circuitry for the embedded trace macrocell for recording selectable aspects of the non-intrusively monitored software execution; and

breakpoint generating instruction associated between the debugging mechanism and the embedded trace macrocell for generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution;

control instructions associated with the debugging mechanism for initiation a non-intrusive debugging process in response to the at least one breakpoint.

12. The digital signal processor debugging system of claim 11, further comprising generating at least one record in response to a predetermined set of profiling counts.

13. The digital signal processor debugging system of claim 11, further comprising a selectable number of threads of the digital signal processor.

14. The digital signal processor debugging system of claim 11, further comprising generating in response to a program counter value a trigger for initiating the non-intrusive debugging process.

15. The digital signal processor debugging system of claim 11, further comprising generating a trigger for initiating the non-intrusive debugging process in response to a load/store address used in the software execution.

16. The digital signal processor debugging system of claim 11, further comprising generating a plurality of records in response to a sequence of events occurring in the software execution.

17. The digital signal processor debugging system of claim 11, further comprising generating at least one record in response to an external event occurring in relation to the software execution.

18. The digital signal processor debugging system of claim 11, further comprising a JTAG interface for programming the operation of the non-intrusive monitoring and the recording instructions and the associated circuitry.

19. The digital signal processor debugging system of claim 11, a packet stream of records derived from the recording instructions and the associated circuitry to transmit to a recording medium.

20. The digital signal processor debugging system of claim 11, further comprising an embedded trace buffer for storing a packet stream of records derived from use of the recording instructions and the associated circuitry.

21. A digital signal processor for operation in support of a personal electronics device, the digital signal processor comprising debugging means for capturing real-time information relating to software execution flow in the digital signal processor and, in response thereto, performing a plurality of non-intrusive debugging operations, the debugging means comprising:

means for operating a non-intrusive debugging process within a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processing process operating on a core processor of the digital signal processor;

means for non-intrusively monitoring software execution in real time for predetermined aspects of software execution associated with the core processing process and occurring in real-time on the core processor;

means for recording selectable aspects of the non-intrusively monitored software execution;

means for generating at least one breakpoint in response to events arising within the means for recording selectable aspects of the non-intrusively monitored software execution; and

means for controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint.

22. The digital signal processor of claim 21, further comprising means for generating at least one record in response to a predetermined set of profiling counts.

23. The digital signal processor of claim 21, further comprising means for selecting a number of threads of the digital signal processor.

24. The digital signal processor of claim 21, further comprising means for generating in response to a program counter value a trigger for initiating the non-intrusive debugging process.

25. The digital signal processor of claim 21, further comprising means for generating a trigger for initiating the non-intrusive debugging process in response to a load/store address used in the software execution.

26. The digital signal processor of claim 21, further comprising means for generating a plurality of records in response to a sequence of events occurring in the software execution.

27. The digital signal processor of claim 21, further comprising means for generating at least one record in response to an external event occurring in relation to the software execution.

28. The digital signal processor of claim 21, further comprising means for programming the operation of the non-intrusive monitoring and the means for recording using a JTAG interface.

29. The digital signal processor of claim 21, further comprising means for generating a packet stream of records derived from the means for recording to transmit to a recording medium.

30. The digital signal processor of claim 21, further comprising means for generating a packet stream of records derived from the means for recording to transmit to an embedded trace buffer recording medium.

31. A computer usable medium having computer readable program code means embodied therein for debugging a multi-threaded digital signal processor including capturing real-time information relating to software execution flow in a processor, the computer usable medium comprising:

computer readable program code means for operating a non-intrusive debugging process within a debugging mechanism of the digital signal processor, the debugging mechanism associated with a core processor;

computer readable program code means for non-intrusively monitoring software execution in real time for predetermined aspects of software execution associated with q core processing process and occurring in real-time on the digital signal processor;

computer readable program code means for recording selectable aspects of the non-intrusively monitored software execution;

computer readable program code means for generating at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution; and

computer readable program code means for controlling aspects of the non-intrusive debugging process in response to the at least one breakpoint.

32. The computer usable medium of claim 31, further comprising computer readable program code means for selecting a number of threads of the digital signal processor.

33. The computer usable medium of claim 31, further comprising computer readable program code means for generating a packet stream of records derived from the computer readable program code means for recording to transmit to an embedded trace buffer recording medium.