METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR DEBUGGING DURING POWER TRANSITIONS
First Claim
1. A method for transferring data between a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, comprising;
- associating a plurality of debugging registers with a core processor process and a debugging process;
setting at least one register control bit within a plurality of debugging registers to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and between the core processor process and the debugging process when a power transition sequence occurrs within the digital signal processor; and
setting at least one power control bit associated with within the plurality of debugging registers to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor when transferring data among the plurality of debugging registers and the core processor process or the debugging process.
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Accused Products
Abstract
Techniques for the design and use of a digital signal processor, including (but not limited to) fox processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.
36 Citations
32 Claims
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1. A method for transferring data between a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, comprising;
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associating a plurality of debugging registers with a core processor process and a debugging process; setting at least one register control bit within a plurality of debugging registers to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and between the core processor process and the debugging process when a power transition sequence occurrs within the digital signal processor; and setting at least one power control bit associated with within the plurality of debugging registers to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor when transferring data among the plurality of debugging registers and the core processor process or the debugging process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A digital signal processor debugging system for operation in association with a digital signal processor in transferring data among a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, the system comprising:
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a plurality of debugging registers associated with a core processor process and a debugging process; at least one register control bit established within the plurality of debugging registers for controlling transferring data among the plurality of debugging registers, the core processor process and the debugging process; the at least one register control bit capable of being set to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and the at least one power control bit further capable of being set to prevent a prevent power transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality Of debugging registers and the core processor process or the debugging process. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A digital signal processor for operation in support of a personal electronics device, the digital signal processor comprising means for transferring data among a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, the digital signal processor comprising:
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means for establishing within the plurality of debugging registers at least one register control bit for controlling transferring data among the plurality of debugging registers and a core processor process and a debugging process; means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and means for setting the at least one power control bit to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 32)
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31. A computer usable medium having computer readable program code means embodied therein for processing instructions on the digital signal processor for debugging a multi-threaded digital signal processor, the computer usable medium comprising:
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computer readable program code means for associating a plurality of debugging registers with a core processor process and a debugging process; computer readable program code means for establishing within the plurality of debugging registers at least one register control bit for controlling transferring data among the plurality of debugging registers and the core processor process and the debugging process; computer readable program code means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and computer readable program code means for setting the at least one power control bit to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.
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Specification