METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR DEBUGGING DURING POWER TRANSITIONS

• US 20080115145A1
• Filed: 11/15/2006
• Published: 05/15/2008
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Pyla, Manojkumar, Chen, Xufeng, Anderson, William C., Codrescu, Lucian, Venkumahanti, Suresh, Giannini, Louis Achille
• Granted Patent: US 7,657,791 B2
• Time in Patent Office: Days
• US Class Current: 719/312
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) fox processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

Claims

1. A method for transferring data between a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, comprising;

associating a plurality of debugging registers with a core processor process and a debugging process;

setting at least one register control bit within a plurality of debugging registers to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and between the core processor process and the debugging process when a power transition sequence occurrs within the digital signal processor; and

setting at least one power control bit associated with within the plurality of debugging registers to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor when transferring data among the plurality of debugging registers and the core processor process or the debugging process.

2. The method of claim, 1, wherein a prevent/transfer value prevents transferring data among the plurality of debugging registers, the core processor process and the debugging process when a power-up sequence occurs.

3. The method of claim 1, further comprising:

setting the at least one register control bit to the prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process when a power-down sequence occurring with the digital signal processor; and

setting the at least one power control bit to the prevent-power-transition value for preventing the power-down sequence of the digital signal processor when transferring data among the plurality of debugging registers and the core processor process or the debugging process.

4. The method of claim 1, wherein the debugging registers comprise a plurality of debugging configuration register and further comprising:

setting the at least one register control bit to the prevent-transfer value for preventing transferring data among the plurality of debugging configuration registers and the core processor process and the debugging process when the power transition sequence occurring with the digital signal processor; and

setting the at least one power control bit to the prevent-power-transition value for preventing the power transition sequence of the digital signal processor when transferring data among the plurality of debugging configuration registers and the core processor process or the debugging process.

5. The method of claim 1, further comprising the step of confirming the debugging process to be a trusted debugging process.

6. The method of claim 1, wherein the pre vent-transfer value comprises an invalid status value and further comprising the step of invalidating read/write transfers among the debugging registers and the core processor process or the debugging process in the event of a power-up sequence of the core processor in response to the invalid status value.

7. The method of claim 1, wherein the prevent-transfer value comprises an invalid status value and further comprising the step of invalidating read/write transfers among the debugging registers and the core processor process or the debugging process in the event of power-down sequence of the core processor in response to the invalid status value.

8. The method of claim 1, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising the step of disabling a power collapse during read/write transfers among the debugging registers and the core processor process or the debugging process in response to the interrupt-disabled value.

9. The method of claim 1, further comprising setting the at least one register control bit to a permit-transfer value for permitting transferring data among the plurality of debugging registers and the core processor process and the debugging process following a power-up sequence occurring with the digital signal processor.

10. The method of claim 1, further comprising the step of setting the at least one power control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal, processor following the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

11. A digital signal processor debugging system for operation in association with a digital signal processor in transferring data among a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, the system comprising:

a plurality of debugging registers associated with a core processor process and a debugging process;

at least one register control bit established within the plurality of debugging registers for controlling transferring data among the plurality of debugging registers, the core processor process and the debugging process;

the at least one register control bit capable of being set to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and

the at least one power control bit further capable of being set to prevent a prevent power transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality Of debugging registers and the core processor process or the debugging process.

12. The digital signal processor debugging system of claim 11, further comprising circuitry and instructions for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power-up sequence occurring with the digital signal processor.

13. The digital signal processor debugging system of claim 11, further comprising:

at least one register control bit for being set to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power-down sequence occurring with the digital signal processor; and

at least one power control bit for being set to a prevent-power-transition value for preventing a power-down sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

14. The digital signal processor debugging system of claim 11, wherein the debugging registers comprise a plurality of debugging configuration registers, and further comprising:

at least one register control bit for being set to a prevent-transfer value for preventing transferring data among tire plurality of debugging configuration registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and

at least one power control bit for being set to a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging configuration registers and the core processor process or the debugging process.

15. The digital signal processor debugging system of claim 11, further comprising a trusted debugging process register for providing at least one trusted debugging control bit in confirming the debugging process to be a trusted debugging process.

16. The digital signal processor debugging system of claim 11, wherein the prevent-transfer value comprises an invalid status value and further comprising circuitry and instructions for invalidating read/write transfers among the debugging registers, the core processor process and the debugging process in the event of a power-up sequence of the core processor in response to the invalid status value.

17. The digital signal processor debugging system of claim 11, wherein the prevent-transfer value comprises an invalid status value and further comprising circuitry and instructions for invalidating read/write transfers among the debugging registers and the core processor process or the debugging process in the event of power-down sequence of the core processor in response to the invalid status value.

18. The digital signal processor debugging system of claim 11, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising further comprising circuitry and instructions for disabling a power collapse during read/write transfers among the debugging registers, the core processor process, and the debugging process in response to the interrupt-disabled value.

19. The digital signal processor debugging system of claim 11, setting the at least one register control bit to a permit-transfer value for permitting transferring data among the plurality of debugging registers and the core processor process and the debugging process following a power-up sequence occurring with the digital signal processor.

20. The digital signal processor debugging system of claim 11, further, comprising instructions and circuitry for setting the at least one power control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal processor following the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

21. A digital signal processor for operation in support of a personal electronics device, the digital signal processor comprising means for transferring data among a plurality of debugging registers and a plurality of digital signal processor processes in association with a power transition sequence of the digital signal processor, the digital signal processor comprising:

means for establishing within the plurality of debugging registers at least one register control bit for controlling transferring data among the plurality of debugging registers and a core processor process and a debugging process;

means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and

means for setting the at least one power control bit to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

22. The digital signal processor system of claim 21, further comprising means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power-up sequence-occurring with the digital signal processor.

23. The digital signal processor system of claim 21, further comprising:

means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power-down sequence occurring with the digital signal processor; and

means for setting the at least one power-control bit to prevent power transition value for preventing a power-down sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

24. The digital signal processor system of claim 21, wherein the debugging registers comprise a plurality of debugging configuration registers, and further comprising:

means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging configuration registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and

means for setting the at least one power control bit to prevent a prevent power transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging configuration registers and the core processor process or the debugging process.

25. The digital signal processor system of claim 21, further comprising means for confirming the debugging process to be a trusted debugging process.

26. The digital signal processor system of claim 21, wherein the prevent-transfer value comprises an invalid status value and further comprising means for invalidating read/write transfers among the debugging registers and the core processor process or the debugging process in the event of a power-up sequence of the core processor in response to the invalid status value.

27. The digital signal processor system of claim 21, wherein the prevent-transfer value comprises an invalid status value and further comprising means for invalidating read/write transfers among the debugging registers and the core processor process or the debugging process in the event of power-down sequence of the core processor in response to the invalid status value.

28. The digital signal processor system of claim 21, wherein the prevent-power-transition value comprises an interrupt-disabled value and further comprising means for disabling a power collapse during read/write transfers among tire debugging registers and the core processor process or the debugging process in response to the interrupt-disabled value.

29. The digital signal processor system of claim 21, further comprising means for setting the at least one register control bit to a permit-transfer value for permitting transferring data among the plurality of debugging registers, the core processor process and the debugging process following a power-up sequence occurring with the digital signal processor.

30. The digital signal processor system of claim 21, further comprising means for setting the at least one register control bit to a permit-power-transition value for permitting a power transition sequence of the digital signal processor following the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

32. The computer usable medium of claim 28, further comprising:

computer readable program code means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and tire core processor process and the debugging process in the event of a power-down sequence Occurring with the digital signal processor; and

computer readable program code means for setting the at least, one power control bit to prevent power transition value for preventing a power-down sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.

31. A computer usable medium having computer readable program code means embodied therein for processing instructions on the digital signal processor for debugging a multi-threaded digital signal processor, the computer usable medium comprising:

computer readable program code means for associating a plurality of debugging registers with a core processor process and a debugging process;

computer readable program code means for establishing within the plurality of debugging registers at least one register control bit for controlling transferring data among the plurality of debugging registers and the core processor process and the debugging process;

computer readable program code means for setting the at least one register control bit to a prevent-transfer value for preventing transferring data among the plurality of debugging registers and the core processor process and the debugging process in the event of a power transition sequence occurring with the digital signal processor; and

computer readable program code means for setting the at least one power control bit to prevent a prevent-power-transition value for preventing a power transition sequence of the digital signal processor in the event of transferring data among the plurality of debugging registers and the core processor process or the debugging process.