METHOD OF FABRICATING SEMICONDUCTOR-BASED POROUS STRUCTURE

• US 20080115913A1
• Filed: 10/31/2007
• Published: 05/22/2008
• Est. Priority Date: 09/16/2005
• Status: Abandoned Application

• Current Assignee: University of Cincinnati
• Original Assignee: University of Cincinnati
• Inventors: Shuja, Ahmed, Medis, Praveen, Parimi, Srinivas, Henderson, H. Thurman, Gerner, Frank M.
• Application Number:
  US11/933,000
• Publication Number:
  US 20080115913A1
• Time in Patent Office: Days
• US Class Current: 165/104.26
• CPC Class Codes: F28D 15/043 forming loops, e.g. capillary pumped loops
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10S 165/218 Condensor adapted to cover opening at top of vapor generator
• CPC Class Codes: Y10T 29/49396 Condenser, evaporator or vaporizer making

Abstract

The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotrophic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (μLHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60w/cm²). The operation is dependent upon a unique micropatterened CPS wick which contains up to millions per square centimeter of stacked uniform micro-through-capillaries in semiconductor-grade silicon, which serve as the capillary “engine,” as opposed to the stochastic distribution of pores in the typical heat pipe wick. As with all heat pipes, cooling occurs by virtue of the extraction of heat by the latent heat of phase change of the operating fluid into vapor.

In the cooling of a laptop computer processor the device could be attached to the processor during laptop assembly. Consistent with efforts to miniaturize electronics components, the current invention can be directly integrated with a unpackaged chip. For applications requiring larger cooling surface areas, the planar evaporators can be spread out in a matrix and integrally connected through properly sized manifold systems.

Claims

1. A fabrication method of making coherent pores in a semiconductor substrate, the fabrication method, comprising:

heavily doping a back surface of a semiconductor substrate via dopant diffusion;

passivating a front surface of the semiconductor substrate with silicon nitride via low pressure chemical vapor deposition (LPCVD);

forming a photoresist pattern on the front surface of the semiconductor substrate through a photolithography process;

wherein the photoresist pattern determines the regions of the semiconductor substrate where pores are to be formed;

selectively etching the silicon nitride via reactive ion etching (RIE) to remove silicon nitride from regions of the semiconductor where pores are to be formed;

depositing a metallic layer on the back surface of the semiconductor substrate and removing the metallic layer from regions of the semiconductor where pores are to be formed via liftoff photolithography;

anisotropically etching the regions of the semiconductor substrate where pores are to be formed from the front surface with an aqueous solution;

applying a bias between the semiconductor substrate and an electrolyte in which the semiconductor substrate is immersed;

illuminating the back surface of the semiconductor substrate; and

providing energy to dislodge hydrogen bubbles from the pores formed during etching of the semiconductor substrate by the electrolyte

2. The method of claim 1, further comprising heavily doping the back surface of the semiconductor substrate via one or more of N+ diffusion and P+ diffusion.

3. The method of claim 1, wherein the silicon nitride is low stress silicon nitride.

4. The method of claim 1, wherein the RIE is performed with a halogen and oxygen gas mixture.

5. The method of claim 1, wherein the metallic layer comprises a layer of gold film.

6. The method of claim 5, wherein the metallic layer comprises a layer of chromium film in contact with the back surface of the semiconductor substrate and the layer of gold film in contact with the layer of chromium film.

7. The method of claim 6, wherein the liftoff photolithography further comprises infrared alignment of photoresist pattern on the back surface with a mask that defines the photoresist pattern on the front surface of the semiconductor substrate.

8. The method of claim 1, wherein the aqueous solution is potassium hydroxide (KOH).

9. The method of claim 1, wherein electrolyte comprises substantially of, hydrofluoric acid dissolved in dimethyl formamide (DMF) and tetra-butyl ammonium percolate (TBAP).

10. The method of claim 1, further comprising illuminating the back surface of the semiconductor substrate with UV light.

11. The method of claim 10, further comprising, providing ultrasonic energy via coupling ultrasonic waves generated by a sonotrode to the electrolyte.

12. The method of claim 11, further comprising applying a positive voltage potential between an n-type semiconductor and the electrolyte;

wherein the n-type semiconductor comprises substantially of n-type CMOS-grade silicon.

13. A method of etching a semiconductor substrate to form pores, the etching method, comprising:

applying a voltage potential between the semiconductor substrate and an electrolyte;

wherein the semiconductor substrate is immersed in the electrolyte;

illuminating a back surface of the semiconductor substrate to create electron-hole pairs in the semiconductor substrate; and

providing energy to dislodge hydrogen bubbles from the pores formed during etching of the semiconductor substrate by the electrolyte.

14. The method of claim 13 wherein the electrolyte is a hydrofluoric acid-based electrolyte.

15. The method of claim 13, wherein the hydrofluoric acid-based electrolyte further comprises one or more of, dimethyl formamide (DMF) and tetra-butyl ammonium percolate (TBAP).

16. The method of claim 13, further comprising applying a positive voltage potential between an n-type semiconductor substrate and the electrolyte;

wherein the n-type semiconductor substrate comprises substantially of n-type CMOS-grade silicon

17. The method of claim 13, further comprising illuminating the back surface of the semiconductor substrate with UV light.

18. The method of claim 13, further comprising, providing ultrasonic energy via coupling ultrasonic waves generated by a sonotrode to the electrolyte.

19. A method of fabricating a microfluidics assembly, the fabrication method, comprising:

cleaning a surface of a substrate having an orifice where a connection to a metallic channel is to be made;

evaporating a first metallic seed layer on the surface;

evaporating a second metallic layer on the first metallic seed layer;

substantially aligning the metallic channel to the orifice of the substrate; and

applying heat and solder material to a junction of the metallic channel and the orifice of the substrate and securing the interconnect.

20. The method of claim 19, wherein the cleaning of the surface comprises:

cleaning the surface with a solvent;

cleaning the surface with a base mixture; and

cleaning the surface with an acidic mixture.

21. The method of claim 19, wherein the first metallic seed layer comprise substantially of, one or more of, Cr and Ti.

22. The method of claim 19, wherein the second metallic layer comprise substantially of, one or more of, Ni, Au, Cu, and Sn.

23. The method of claim 19, further comprising, removing oxide from the metallic channel.

24. A method of fabricating a microfluidics assembly, the fabrication method, comprising:

cleaning a surface of a substrate having an orifice where a connection to a glass channel is to be made;

coating an external surface of the glass channel with a first conductive seed layer;

coating the first conductive seed layer with a second metallic layer;

evaporating a first conductive seed layer on the surface of the substrate;

evaporating a second conductive layer on the first conductive seed layer;

substantially aligning the channel to the orifice of the substrate; and

applying heat to a junction of the glass channel to the orifice of the substrate and securing the interconnect.

25. The method of claim 24, further comprising cleaning the glass channel, the method comprising:

cleaning the surface with a solvent;

cleaning the surface with a base mixture; and

cleaning the surface with an acidic mixture.