SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME

• US 20080116512A1
• Filed: 11/20/2007
• Published: 05/22/2008
• Est. Priority Date: 11/21/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akiyama, Miwako, Yamaguchi, Yoshihiro, Kawaguchi, Yusuke
• Application Number:
  US11/943,181
• Publication Number:
  US 20080116512A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first conductivity type layer and a second conductivity type layer, which are alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate. The balance of the net charge amount of the impurity between the first conductivity type layer formed under a second conductivity type base layer in the termination region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer is imbalanced in comparison to the balance of the net charge amount of the impurity between the first conductivity type layer in the device-forming region of the semiconductor device and the second conductivity type layer adjacent to the first conductivity type layer.

Claims

1. A semiconductor device comprising:

a first conductivity type layer and a second conductivity type layer, each being alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate;

a second conductivity type base layer formed on the first conductivity type layer and the second conductivity type layer;

a trench formed so as to extend from a surface of the second conductivity type base layer to the first conductivity type layer;

a gate insulation film formed on the side surfaces and the bottom surface of the trench;

a gate electrode formed inside the trench via the gate insulation film;

an interlayer insulating film formed on the gate electrode;

a first conductivity type diffusion layer formed on the surface of the second conductivity type base layer;

a first main electrode formed on the first conductivity type diffusion layer;

a second main electrode formed on the bottom surface of the first conductivity type substrate;

a device-forming region in which the first conductivity type diffusion layer is formed; and

a termination region provided around the circumference of the device-forming region and not including the first conductivity type diffusion layer formed therein,

wherein the balance of the net charge amount of the impurity between the first conductivity type layer formed under the second conductivity type base layer in the termination region and the second conductivity type layer adjacent to the first conductivity type layer is imbalanced in comparison to the balance of the net charge amount of the impurity between the first conductivity type layer in the device-forming region and the second conductivity type layer adjacent to the first conductivity type layer.

2. The semiconductor device according to claim 1, wherein

the imbalance of the net charge amount of the impurity between a first conductivity type layer in the termination region and a second conductivity type layer adjacent to the first conductivity type layer is determined, in comparison to the balance of the device-forming region, by providing a difference between the width of the second conductivity type layer in the termination region and the width of the second conductivity type layer in the device-forming region.

3. The semiconductor device according to claim 1, wherein

the imbalance of the net charge amount of the impurity between a first conductivity type layer in the termination region and a second conductivity type layer adjacent to the first conductivity type layer is determined, in comparison to the balance of the device-forming region, by providing a difference between the array pitch of the second conductivity type layer in the termination region and the array pitch of the second conductivity type layer in the device-forming region.

4. The semiconductor device according to claim 1, wherein

the imbalance of the net charge amount of the impurity between a first conductivity type layer in the termination region and a second conductivity type layer adjacent to the first conductivity type layer is determined, in comparison to the balance of the device-forming region, by providing a difference between the impurity concentration of the second conductivity type layer in the termination region and the impurity concentration of the second conductivity type layer in the device-forming region.

5. The semiconductor device according to claim 1, further comprising:

a contacting trench provided in the second conductivity type base layer;

wherein the first main electrode is also formed inside the contacting trench.

6. A method for making a semiconductor device comprising:

forming a first conductivity type layer on a first conductivity type substrate by epitaxial growth;

forming a second conductivity type base layer by injecting and diffusing second conductivity type impurity into a surface of the first conductivity type layer;

forming a trench so as to extend from the surface of the second conductivity type base layer to the first conductivity type layer;

forming a gate insulation film on the side surfaces and the bottom surface of the trench;

forming a gate electrode inside the trench via the gate insulation film;

forming an interlayer insulating film on the gate electrode;

depositing a processing film over the first conductivity type layer in which the second conductivity type base layer is formed;

forming a first aperture in the processing film on a device-forming region, and forming a second aperture in the processing film on a termination region provided around the circumference of the device-forming region;

performing ion implantation on the first conductivity type layer, so that the balance of the net charge amount of the impurity between a second conductivity type layer formed under the second conductivity type base layer in the termination region using the processing film as a mask and the first conductivity type layer adjacent to the second conductivity type layer becomes imbalanced in comparison to the balance of the net charge amount of the impurity between a second conductivity type layer formed under the second conductivity type base layer in the device-forming region and the first conductivity type layer adjacent to the second conductivity type layer;

performing ion implantation on the second conductivity type base layer on the device-forming region to form a first conductivity type diffusion layer;

forming a first main electrode on the first conductivity type diffusion layer; and

forming a second main electrode on the bottom surface of the first conductivity type substrate.

7. The method for making a semiconductor device according to claim 6, wherein

the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the termination region becomes imbalanced in comparison to the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the device-forming region, by providing a difference between the array pitch of a first aperture formed in the processing film on the device-forming region and the array pitch of a second aperture formed in the processing film on the termination region.

8. The method for making a semiconductor device according to claim 6, wherein

the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the termination region becomes imbalanced in comparison to the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the device-forming region, by providing a difference between a first width of a first aperture formed in the processing film on the device-forming region and a second width of a second aperture formed in the processing film on the termination region.

9. The method for making a semiconductor device according to claim 6, wherein

the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the termination region becomes imbalanced in comparison to the balance of the net charge amount of the impurity between the second conductivity type layer and the first conductivity type layer in the device-forming region, by providing a difference between the impurity concentration of the second conductivity type layer in the device-forming region and the impurity concentration of the second conductivity type layer in the termination region.

10. The method for making a semiconductor device according to claim 6, further comprising:

forming a contacting trench in the second conductivity type base layer using the processing film as a mask, the processing film having the first and second apertures; and

forming the first main electrode on the first conductivity type diffusion layer including the inside of the contacting trench.

11. A semiconductor device comprising:

a first conductivity type layer and a second conductivity type layer, each being alternately and repeatedly positioned, adjacent to each other, in a column-like fashion on a first conductivity type substrate;

a second conductivity type base layer formed on the first conductivity type layer and the second conductivity type layer;

a trench formed so as to extend from a surface of the second conductivity type base layer to the first conductivity type layer;

a gate insulation film formed on the side surfaces and the bottom surface of the trench;

a gate electrode formed inside the trench via the gate insulation film;

an interlayer insulating film formed on the gate electrode;

a first conductivity type diffusion layer formed on the surface of the second conductivity type base layer;

a first main electrode formed on the first conductivity type diffusion layer;

a second main electrode formed on the bottom surface of the first conductivity type substrate;

a device-forming region in which the first conductivity type diffusion layer is formed; and

a termination region provided around the circumference of the device-forming region and not including the first conductivity type diffusion layer formed therein;

wherein the second conductivity type base layer in the device-forming region has a higher second conductivity type impurity concentration in a position far from the trench than in the vicinity of the trench.

12. The semiconductor device according to claim 11, wherein

the impurity concentration of the second conductivity type base layer has a concentration distribution with a substantially maximum concentration in the substantially middle of the trench.