Termination Structures For Semiconductor Devices and the Manufacture Thereof

• US 20080116520A1
• Filed: 05/21/2004
• Published: 05/22/2008
• Est. Priority Date: 05/31/2003
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Grover, Raymond J.
• Application Number:
  US10/561,308
• Publication Number:
  US 20080116520A1
• Time in Patent Office: Days
• US Class Current: 257/362
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/866 Zener diodes

Abstract

A semiconductor device has a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area. The termination structure comprises a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode. The termination structure (16) is capable of withstanding higher voltages in a compact manner and features thereof are susceptible to fabrication in the same process steps as features of the active area (7).

Claims

1. A semiconductor device having a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area, the termination structure comprising a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode.

2. A semiconductor device of claim 1 wherein a zener diode (8) is connected between each pair of adjacent lateral transistors (2a to 2d).

3. A semiconductor device of claim 2 wherein each zener diode (8) is connected between the source electrode (10) of the lateral transistor of the corresponding pair closer to the active area (7) and the gate electrode (4) of the other lateral transistor of the corresponding pair.

4. A semiconductor device of claim 2 wherein each zener diode (8) is connected between the gate electrodes (4) of the corresponding pair of lateral transistors.

5. A semiconductor device of any preceding claim wherein each lateral device (2a to 2d) comprises a gate electrode (31) insulated from the semiconductor body (22) by a layer (32) of gate insulating material, the gate electrodes and layers of gate insulating material of the lateral devices being formed in the same respective process steps as insulated electrodes (11) and layers (25) of material insulating the insulated electrodes of devices in the active area (7).

6. A semiconductor device of claim 5 wherein the active area (7) comprises trench-gate semiconductor devices and the lateral transistors of the termination structure (16) are trench-gate transistors.

7. A semiconductor device of claim 5 or claim 6 wherein each lateral device (2a to 2d) comprises a trench (30) having the gate electrode (31) therein, the trenches of the lateral devices being formed in the same respective process steps as gate trenches (20) of devices in the active area (7).

8. A semiconductor device of claim 5 wherein the active area (7) comprises planar gate semiconductor devices and the lateral transistors of the termination structure (16) are planar gate transistors.

9. A semiconductor device of any preceding claim wherein the lateral devices (2a to 2d) include a region (15) of a first conductivity type over an underlying region (14a) of a second, opposite conductivity type, and wherein the active area (7) comprises devices having a region (15) of the first conductivity type which is formed in the same process step as the first conductivity type region of the lateral devices.

10. A semiconductor device of any preceding claim wherein the gate electrodes (31) of the lateral devices are formed of polycrystalline silicon, and the zener diode (8) is formed of polycrystalline silicon deposited in the same process step as the gate electrodes.

11. A method of forming a semiconductor device having a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area, the termination structure comprising a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode, wherein the gate electrodes (31) of the lateral devices are formed of polycrystalline silicon, and the method comprises forming the zener diode (8) of polycrystalline silicon deposited in the same process step as the gate electrodes.

12. A method of claim 11 wherein each lateral device (2a to 2d) comprises a trench (30) having the gate electrode (31) therein, and the method comprises forming the trenches of the lateral devices in the same respective process steps as gate trenches (20) of devices in the active area (7).

13. A semiconductor device substantially as described herein with reference to the accompanying Drawings.

14. A method of forming a semiconductor device substantially as described herein with reference to the accompanying Drawings.