CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC

• US 20080116537A1
• Filed: 11/17/2006
• Published: 05/22/2008
• Est. Priority Date: 11/17/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Gambino, Jeffrey P., Rassel, Richard J., Sprogis, Edmund J., Leidy, Robert K., Jaffe, Mark D., Adkisson, James W., Luce, Stephen E.
• Granted Patent: US 7,781,781 B2
• Time in Patent Office: Days
• US Class Current: 257/448
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.

Claims

1. A CMOS imager array comprising:

a substrate;

an array of light receiving pixel structures formed above said substrate, said array having formed therein “

m”

levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer;

a dense logic wiring region formed adjacent to said array of light receiving pixel structures having “

n”

levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>

m.

2. The imager array as claimed in claim 1, wherein said array of light receiving pixel structures comprises:

a microlens array having microlenses and color filters formed above said interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of said substrate.

3. The imager array as claimed in claim 2, wherein a top surface of said interlevel dielectric material layer beneath microlens array is recessed from a top surface of said interlevel dielectric material layers of said dense logic wiring region.

4. The imager array as claimed in claim 2, wherein a dense logic wiring region is formed at two opposing sides adjacent said pixel array region, said dense logic wiring region including a passivation layer formed at a top surface and having a final conductive structure.

5. The imager array as claimed in claim 1, wherein said “

n”

levels of conductive structures at said dense logic wiring region are interconnected by via structures.

6. The imager array as claimed in claim 4, further comprising:

a protective structure mounted to a top surface of said passivation structure at said two opposing sides, said protective structure and a top surface of said microlens array separated by a gap, wherein said gap providing additional protection of said microlens array during mounting of said protective structure.

7. The imager array as claimed in claim 6, wherein said mounted protective structure comprises a glass plate covering said array of light receiving pixel structures.

8. The imager array as claimed in claim 6, wherein said gap is about 10 microns or greater in thickness.

9. The imager array as claimed in claim 6, further including a conductive element electrically connecting said final conductive structure of said dense logic wiring region to an external conductor.

10. The imager array as claimed in claim 9, wherein said conductive element is a bond wire.

11. The imager array as claimed in claim 9, wherein said external conductor includes a solder element formed beneath said substrate as part of a ball grid array structure.

12. The imager array as claimed in claim 11, wherein said ball grid array structure is formed as part of a Schott integrated circuit package.

13. The imager array as claimed in claim 11, wherein said ball grid array structure is formed as part of a Shellcase integrated circuit package.

14. The imager array as claimed in claim 1, where m=2 and n≧

4.

15. The imager array as claimed in claim 1, where m≦

4 and n≧

4.

16. A method for fabricating an image sensor array of pixels comprising the steps of:

forming a plurality of light sensitive elements in a semiconductor substrate to form a pixel array region of said sensor array;

forming a stack of “

m”

interlevel dielectric material layers atop said substrate in both said pixel array region of said sensor array and an adjacent dense wiring logic region of said sensor array, each said “

m”

interlevel dielectric material layers including a respective metal interconnect level comprising a conductor structure in both said pixel array region of said sensor array and said adjacent dense wiring logic region of said sensor array;

forming a stack of additional interlevel dielectric layers atop said “

m”

interlevel dielectric material layers over both said pixel array region and said dense logic wiring region, said stack of additional interlevel dielectric layers formed in said adjacent dense logic wiring region including respective additional metal interconnect levels including additional metal level conductor structures formed only in said adjacent dense logic wiring region, wherein a total of “

n”

metal interconnect levels having conductive structures is formed in said adjacent dense logic wiring region, wherein n>

m;

removing a portion of said additional interlevel dielectric layers formed atop pixel array region whereby a surface of said additional interlevel dielectric layers in said pixel array region is recessed from a top surface of said additional interlevel dielectric material layers of said dense logic wiring region; and

,

forming a microlens array having microlenses and color filters above said recessed surface of said interlevel dielectric material layer in said pixel array region, a microlens and respective color filter in alignment with a respective light sensitive element.

17. The method as claimed in claim 16, wherein said removing of a portion of said additional interlevel dielectric layers in said pixel array region is an etchback process.

18. The method as claimed in claim 17, wherein said etchback process for removing of a portion of said additional interlevel dielectric layers of said pixel array region comprises:

applying a mask structure lithographically patterned to expose only a surface of said additional interlevel dielectric layers formed atop pixel array region pixel; and

,

conducting an etch process to selectively remove portions of the additional interlevel dielectric layer in said pixel array region;

19. The method as claimed in claim 16, wherein said step of forming a stack of additional interlevel dielectric layers atop said “

m”

interlevel dielectric material layers in said pixel array region further comprises;

forming an etch stop layer extending across said pixel array region, wherein said step of conducting an etch process includes terminating said etch of additional interlevel dielectric layers at said etch stop layer.

20. The method as claimed in claim 16, wherein said conductor structures of said respective metal interconnect levels comprises a copper material, each said conductor structures including a barrier material layer formed atop each said conductor structure.

21. The method as claimed in claim 16, wherein said dense logic wiring region is formed at two opposing sides adjacent said pixel array region, said method further comprising:

forming a passivation structure at a top surface of each said dense logic wiring region having a final conductive structure.

22. The method as claimed in claim 21, further comprising:

mounting a protective structure to a top surface of said passivation structure at said two opposing sides, said protective structure and a top surface of said microlens array separated by a gap, said gap providing additional protection of said microlens array during said mounting.

23. The method as claimed in claim 22, further including:

connecting a conductive element to electrically connect said final conductive structure of said dense logic wiring region to an external conductor.

24. The method as claimed in claim 23, wherein said external conductor includes a solder element formed beneath said substrate as part of a ball grid array structure.

25. The method as claimed in claim 24, further comprising forming a Schott integrated circuit package for housing said imager sensor array.

26. The method as claimed in claim 24, further comprising forming a Shellcase integrated circuit package for housing said imager sensor array.