METHOD OF PACKAGING A DEVICE HAVING A TANGIBLE ELEMENT AND DEVICE THEREOF

• US 20080116560A1
• Filed: 11/17/2006
• Published: 05/22/2008
• Est. Priority Date: 11/17/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mangrum, Marc A., Burch, Kenneth R.
• Granted Patent: US 7,696,016 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. An insulating layer is formed over the first major surface. A via is formed in the insulating layer. A tangible element is coupled to the semiconductor device through the via. At least a portion of the tangible element is surrounded with a cavity wall having a first face toward the element and a second face away from the element. A supporting layer, after surrounding the tangible element, is formed over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face thereby providing protection for the tangible element.

Claims

1. A method of forming a packaged device having a semiconductor device having a first major surface and a second major surface, comprising:

forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the semiconductor device exposed,

forming an insulating layer over the first major surface;

forming a via in the insulating layer;

coupling a tangible element to the semiconductor device through the via;

surrounding at least a portion of the tangible element with a cavity wall having a first face toward the tangible element and a second face away from the tangible element;

forming a supporting layer, after the step of surrounding the tangible+element, over the insulating layer so that the supporting layer is adjacent to the second face and blocked from the first face.

2. The method of claim 1, further comprising:

removing the cavity wall after the step of depositing the supporting layer.

3. The method of claim 2, wherein the step of forming the supporting layer comprises:

depositing a liquid; and

curing the liquid prior to the step of removing.

4. The method of claim 3, wherein the step of depositing a liquid is further characterized by the liquid comprising an epoxy resin.

5. The method of claim 1, wherein the step of surrounding is further characterized by the cavity wall having a top portion over the at least a portion of the tangible element.

6. The method of claim 5, further comprising removing at least a portion of the top portion to expose the tangible element.

7. The method of claim 6, wherein the step of removing at a least a portion is further characterized as comprising one of a group consisting of sawing, laser cutting, and grinding.

8. The method of claim 1, wherein the step of coupling a tangible element is further characterized by the tangible element comprising one of a group consisting of a camera, a speaker, a sensor, a switch, a light-emitting diode, a microphone, and a contact.

9. The method of claim 1, wherein the step of coupling the tangible element is further characterized by the tangible element being over the semiconductor device.

10. The method of claim 1, wherein the step of coupling the tangible element is further characterized by the tangible element being laterally adjacent to the semiconductor device.

11. A packaged semiconductor device comprising

a semiconductor device having a first major surface and a second major surface;

an encapsulant over the second major surface and around sides of the semiconductor device,

an insulating layer over the first major surface;

a via in the insulating layer;

a tangible element coupled to the semiconductor device through the via;

a wall surrounding at least a portion of the tangible element

a supporting layer laterally surrounding the wall.

12. The packaged semiconductor device of claim 11, wherein:

the supporting layer has a top surface above the at least a portion of the tangible element; and

a region extending from the top surface to the at least a portion of the tangible element is open.

13. The packaged semiconductor device of claim 11, wherein:

the tangible element comprises one of a group consisting of a camera, a speaker, a sensor, a switch, a light-emitting diode, a microphone, and a contact;

14. The packaged semiconductor device of claim 11, wherein the supporting layer comprises epoxy resin.

15. The method of claim 11, wherein the tangible element is further characterized as being over the semiconductor device and under the insulating layer. +

16. The method of claim 11, wherein tangible element is further characterized as being laterally adjacent to the semiconductor device and under the insulating layer.

17. A method of forming a packaged device having a semiconductor device having a first major surface and a second major surface, comprising:

forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the semiconductor device exposed,

forming an insulating layer over the first major surface;

forming a via in the insulating layer;

coupling a tangible element to the semiconductor device through the via;

surrounding at least a portion of the tangible element with a protective means for preventing a subsequently formed supporting layer from contacting the tangible element;

forming the supporting layer, after the step of surrounding at least a portion of the tangible element, over the insulating layer and in contact with the protective means.

18. The method of claim 17, wherein:

the step of surrounding comprises forming a wall over the insulating layer and around the at least a portion of the tangible element;

the step of coupling is further characterized by the tangible element being over the insulating layer and comprising one of a group consisting of a contact and a transducer.

19. The method of claim 18, wherein the step of surrounding is further characterized by the wall having a top portion covering the at least a portion of the tangible element, further comprising removing at least a portion of the top portion to expose the tangible element.

20. The method of claim 19, wherein the step of forming the supporting layer comprises:

applying an epoxy resin in liquid form; and

curing the epoxy resin.