Apparatus for mass die testing

• US 20080116910A1
• Filed: 11/17/2006
• Published: 05/22/2008
• Est. Priority Date: 11/17/2006
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hung, Tsung-Yang
• Application Number:
  US11/600,973
• Publication Number:
  US 20080116910A1
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

A semiconductor wafer includes a set of dice under test connected together by a plurality of signal buses; and at least one test die designed for carrying out tests of the dice under test, having a set of pads to be connected to one or more probes of an external test apparatus, and at least one multiplexer connected with the set of dice under test via the signal buses, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.

Claims

1. A semiconductor wafer comprising:

a set of dice under test (DUT) connected together by a plurality of signal buses; and

at least one built-in self test (BIST) die including at least one multiplexer designed for multiplexing test signals to a selected DUT on the semiconductor wafer for carrying out tests of the dice under test, the BIST die having a set of pads to be connected to one or more probes of an external test apparatus, and

wherein the at least one multiplexer being connected with the set of dice under test via the signal buses, such that the BIST die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes.

2. The semiconductor wafer of claim 1 wherein the set of pads comprises one or more test probing pads for receiving test signals from the external test apparatus via the probes.

3. The semiconductor wafer of claim 1 wherein the set of pads comprises one or more address probing pads for receiving address signals indicating an address of at least one die under test from the external test apparatus via the probes.

4. The semiconductor wafer of claim 1 wherein the set of pads comprises one or more power supply probing pads for receiving power from the external test apparatus via the probes.

5. The semiconductor wafer of claim 1 wherein the signal buses are routed along scribe lines among the dice under test.

6. The semiconductor wafer of claim 5 wherein each die under test has a seal ring with one or more feed-through paths, through which one or more tacks are disposed to form electrical connections between the signal buses and electrical components within the seal ring.

7. The semiconductor wafer of claim 6 wherein the die under test is a radio frequency (RF) chip.

8. A test system comprising:

a semiconductor wafer having a set of dice under test connected together by a plurality of signal buses, and at least one built-in self test BIST die designed for carrying out tests of the dice under test, wherein the BIST includes at least one multiplexer;

a set of probes connected to one or more pads on the BIST die;

a test apparatus coupled to the probes for sending test signals to one or more selected dice under test, and for receiving output signals from the selected dice under test for analysis through the multiplexer,

wherein the multiplexer is connected to the dice under test via the signal buses, such that the BIST die is capable of receiving signals from the test apparatus to select any die under test within the set without repositioning the probes.

9. The system of claim 8 wherein the pads comprise one or more test probing pads for receiving test signals from the test apparatus via the probes, one or more address probing pads for receiving address signals indicating an address of at least one die under test from the test apparatus via the probes, and one or more power supply probing pads for receiving power from the test apparatus via the probes.

10. The system of claim 8 wherein the signal buses are routed along scribe lines among the dice under test.

11. The system of claim 10 wherein each die under test has a seal ring with one or more feed-through paths, through which one or more tacks are disposed to form electrical connections between the signal buses and electrical components within the seal ring.

12. The system of claim 8 wherein the regular die is a radio frequency (RF) chip.

13. The system of claim 12 wherein the set of probes comprises at least two test signal probes for passing test signals, at least three address probes for passing address signals to select one or more dice under test, and at least two power probes for providing the test die with power.

14. The system of claim 13 wherein the test apparatus comprises a control device coupled to the probes for generating the address signals.

15. The system of claim 14 wherein the test apparatus comprises at least one RF tester coupled between the control device and at least one matching module that couples RF signals between the RF tester and an antenna interface for signals output from the test die.

16. The system of claim 15 wherein the matching module is a transformer or an impedance matching circuit constructed by at least one inductor and at least one capacitor.

17. A probe card for testing a set of dice under test on a semiconductor wafer, comprising:

at least one set of probes to be connected to one or more pads or a built-in self test (BIST) die on the semiconductor wafer for providing accesses to the dice under test via signal buses there among;

at least one multiplexer located within the BIST die and coupled to the probes, having one or more ports for receiving and sending signals from and to an external test apparatus;

wherein when the test probes are in contact with the pads and the ports are connected to the external test apparatus, the external test apparatus can select any die under test within the set without repositioning the probes.

18. The probe card of claim 17 wherein the probes comprises at least one radio frequency (RF) probes for passing RF test signals, at least two power probes for providing power, and at least three digital probes for passing address signals.

19. The probe card of claim 17 wherein the signal buses are routed along scribe lines among the dice under test.

20. The probe card of claim 17 wherein each die under test has a seal ring with one or more feed-through paths, through which one or more tacks are disposed to form electrical connections between the signal buses and electrical components within the seal ring.