Embedding Memory within Tile Arrangement of a Configurable IC

• US 20080116931A1
• Filed: 10/28/2007
• Published: 05/22/2008
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Herman Schmit, Jason Redgrave
• Inventors: Redgrave, Jason, Schmit, Herman
• Granted Patent: US 7,652,499 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Claims

1-22. -22. (canceled)

23. A routing fabric for a configurable integrated circuit (IC), wherein said configurable IC comprises memory tiles and computational tiles, said routing fabric comprising:

a) a first set of routing elements placed in an arrangement within a first computational tile; and

b) a second set of routing elements, matching said first set of routing elements, placed within a first memory tile in the same arrangement as said first set of routing elements.