DELAY-LOCKED LOOP CIRCUIT AND METHOD OF GENERATING MULTIPLIED CLOCK THEREFROM

• US 20080116950A1
• Filed: 10/23/2007
• Published: 05/22/2008
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Seung-Hwan, Lee, Seung-Won
• Granted Patent: US 7,602,223 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal in response to the detection signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal using the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal. The multiplied clock signal is generated by multiplying the external clock signal an integer number of times and the feedback clock signal is delayed from the plurality of delay clock signals by a cycle period of the external clock signal.

Claims

1. A delay-locked loop circuit comprising:

a phase detector generating a detection signal by detecting a phase difference between an external clock signal and a feedback clock signal;

a charge pump controlling a level of a voltage signal VCON in response to the detection signal; and

a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal by means of the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal,

wherein the multiplied clock signal is generated by multiplying the external clock signal an integer number of times and wherein the feedback clock signal is delayed from the plurality delay clock signals by a cycle period of the external clock signal.

2. The delay-locked loop circuit as set forth in claim 1, wherein the frequency domain is divided into high and low frequency domains relative to a reference frequency.

3. The delay-locked loop circuit as set forth in claim 2, further comprising:

a frequency detector generating a selection signal dividing the high and low frequency domains in response to the external clock signal,

wherein the voltage-controlled delay line generates the multiplied clock signal in response to the selection signal.

4. The delay-locked loop circuit as set forth in claim 3, wherein the detection signal of the phase detector includes up and down signals.

5. The delay-locked loop circuit as set forth in claim 4, wherein the phase detector comprises:

a first flip flop including an input node to which a driving voltage is applied, a clock node to which the external clock signal is applied, a reset node to which a reset signal is applied, and an output node from which the up signal is output;

a second flip flop including an input node to which a driving voltage is applied, a clock node to which the feedback clock signal is applied, a reset node to which the reset signal is applied, and an output node from which the down signal is output;

a first logic circuit executing a NAND operation with the up and down signals; and

a second logic circuit generating the reset signal from an AND operation with an output value of the first logic circuit and an initializing signal.

6. The delay-locked loop circuit as set forth in claim 4, wherein the charge pump comprises:

a first NMOS transistor including a drain connected to a driving voltage, a source connected to an output terminal, and a gate coupled to the up signal;

a second NMOS transistor including a drain connected to the output terminal, a source connected to a ground, and a gate coupled to the down signal; and

a capacitor coupled between the output terminal and ground.

7. The delay-locked loop circuit as set forth in claim 4, wherein the voltage-controlled delay line generates the plurality of delay clock signals using a plurality of delay cells.

8. The delay-locked loop circuit as set forth in claim 7, wherein each delay cell generates a delay clock signal from an input clock signal using an inverter.

9. The delay-locked loop circuit as set forth in claim 8, wherein each delay cell comprises:

a PMOS transistor including a source connected to the driving voltage, a drain connected to a delay clock output node, and a gate coupled to an input clock;

a third NMOS transistor including a drain connected to the delay clock output node and a gate coupled to the input clock; and

a fourth NMOS transistor including a drain connected to the source of the third NMOS transistor, a source connected to ground, and a gate coupled to the voltage signal.

10. The delay-locked loop circuit as set forth in claim 7, wherein the voltage-controlled delay line comprises 2m delay cells (m is a positive integer), sequentially generates 2m delay clock signals with predetermined delay times each through a respective one of the plurality of delay cells, and determines to generate the multiplied clock signal by means of m delay clock signals or 2m delay clock signals, according to a delayed sequence, in response to a selection signal.

11. The delay-locked loop circuit as set forth in claim 10, wherein the m delay clock signals are used when the external clock signal operates in a high frequency, and 2m delay clock signals are used when the external clock signal operates in low frequency.

12. The delay-locked loop circuit as set forth in claim 11, wherein the voltage-controlled delay line comprises:

a first multiplied clock generator operating to generate a first multiplied clock signal by means of the m-numbered delay clock signals sequentially delayed from the external clock;

a second multiplied clock generator operating to generate a second multiplied clock signal by means of the 2m-numbered delay clock signals; and

a multiplied clock selector operating to select one of the first and second multiplied clock signals in response to the selection signal.

13. The delay-locked loop circuit as set forth in claim 12, wherein the voltage-controlled delay line further comprises:

a plurality of buffers temporarily storing the 2m-numbered delay clock signals,

wherein the delay clock signals stored in the plurality of buffers are transferred to the first and second multiplied clock generators.

14. The delay-locked loop circuit as set forth in claim 12, wherein the first and second multiplied clock generators operate to generate the multiplied clock signal that is a half of the external clock signal in cycle period.

15. The delay-locked loop circuit as set forth in claim 14, wherein m is 4 and the delay clock signals are generated from a first to an eighth in sequence.

16. The delay-locked loop circuit as set forth in claim 15, wherein the first multiplied clock generator comprises:

a first logic circuit executing an XOR operation with a first and second delay clock signals;

a second logic circuit executing an XOR operation with a third and fourth delay clock signals; and

a third logic circuit generating the first multiplied clock signal by executing an XOR operation with output values of the first and second logic circuits.

17. The delay-locked loop circuit as set forth in claim 16, wherein the second multiplied clock generator comprises:

a fourth logic circuit executing an XOR operation with a fifth and sixth delay clock signals;

a fifth logic circuit executing an XOR operation with a seventh and eighth clock signals, a sixth logic circuit executing an XOR operation with output values of the fourth and fifth logic circuits;

a seventh logic circuit executing an XOR operation with output values of the first multiplied clock generator and the sixth logic circuit; and

a frequency divider generating the second multiplied clock signal by dividing an output value of the seventh logic circuit in half.

18. The delay-locked loop circuit as set forth in claim 15, wherein the voltage-controlled delay line further comprises:

a feedback clock selector operating to select one from the fourth and eighth delay clock signals in response to the selection signal.

19. A delay-locked loop circuit comprising:

a phase detector generating a detection signal from a detected phase difference between an external clock signal and a feedback clock signal;

a charge pump controlling a level of a voltage signal in response to the detection signal;

a selection signal generator operating to generate a selection signal, according to a plurality of frequency domains, in response to the detection signal; and

a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal, which is multiplied from the external clock signal by an integer number of times, from the delay clock signals different in number in accordance with the selection signal, wherein the feedback clock signal is delayed from the plurality delay clock signals by a cycle period of the external clock signal.

20. A method of generating a multiplied clock signal from a delay-locked loop circuit, comprising the steps of:

(a) detecting a frequency domain of an external clock signal; and

(b) generating a multiplied clock signal with varying the number of delay cells in accordance with the frequency domain detected by the step (a).

21. The method as set forth in claim 20, wherein the frequency domain is divided into high and low frequency domains relative to a reference frequency and the multiplied clock signal is a half of the external clock signal in cycle period.

22. The method as set forth in claim 21, wherein the multiplied clock signal is generated from half of the delay cells when the external clock signal operates in a high frequency, and the multiplied clock signal is generated from all of the delay cells when the external clock signal operates in a low frequency.