Detection circuit and detection method

• US 20080116970A1
• Filed: 11/22/2006
• Published: 05/22/2008
• Est. Priority Date: 11/22/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Asam, Michael
• Granted Patent: US 7,911,236 B2
• Time in Patent Office: Days
• US Class Current: 330/129
• CPC Class Codes: G01R 19/0084 measuring voltage only all subgroups of G01R19/00 take precedence
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

A detection circuit includes a bias circuit configured to generate a first bias voltage and a second bias voltage. The detection circuit further includes a storage device configured to store a detection value corresponding to an amplitude of a radio frequency signal received at a detector input. A series connection of a first diode element and a second diode element includes first tap to receive the first bias voltage and the radio frequency signal, a second tap which is coupled to a connection node of the first and the second diode element to receive the second bias voltage and a third tap to provide the detection value.

Claims

1. A detection circuit, comprising:

a detector input;

a detector output;

a capacitive element coupled to the detector output;

a bias circuit comprising a first bias output configured to provide a first bias voltage and a second bias output configured to provide a second bias voltage;

a first diode element comprising a first node coupled to the detector input and a second node coupled to the first bias output; and

a second diode element comprising a first node coupled to the second bias output and a second node coupled to the capacitive element and to the second node of the first diode element.

2. The detection circuit of claim 1, wherein at least one of the first and the second diode elements is coupled to their respective bias output via a resistive element.

3. The detection circuit of claim 1, wherein at least one of the first and the second diode elements comprises a transistor.

4. The detection circuit of claim 3, wherein the first diode comprise the transistor, and wherein a control node of the transistor is coupled to a further node of the transistor via a capacitor.

5. The detection circuit of claim 1, wherein the bias circuit comprises a current source and a series connection of a third and a fourth diode element.

6. The detection circuit of claim 5, wherein the third and the fourth diode element each comprise a transistor.

7. The detection circuit of claim 1, wherein the capacitive element comprises a current source or a resistive element, respectively connected in parallel to a capacitor.

8. A detection circuit, comprising:

a bias circuit configured to generate a first bias voltage and a second bias voltage;

a detector input configured to receive a radio frequency signal;

a storage device configured to store a detection value corresponding to an amplitude of the radio frequency signal;

a series connection of a first diode element and a second diode element, the series connection comprising a first tap to receive the first bias voltage and the radio frequency signal, a second tap which is coupled to a connection node of the first and the second diode element to receive the second bias voltage, and a third tap to provide the detection value.

9. The detection circuit of claim 8, wherein at least one of the first and the second bias voltages is received at the first and second taps, respectively, via a resistive coupling.

10. The detection circuit of claim 8, wherein the first and the second diode element each comprise a transistor.

11. The detection circuit of claim 10, wherein the first diode comprises the transistor, and wherein a control node of the transistor element is coupled to a further node of the transistor via a capacitor.

12. The detection circuit of claim 8, wherein the storage device comprises a capacitor and a discharging device connected in parallel with the capacitor.

13. A detection circuit, comprising:

a detector input;

a detector output;

a bias circuit comprising a first bias output configured to provide a first bias voltage and a second bias output configured to provide a second bias voltage;

a first capacitive element comprising a first node coupled to the detector input and a second node coupled to the second bias output;

a second capacitive element comprising a first node coupled to the detector output and a second node which is coupled to a reference voltage tap;

a first diode element comprising a first node coupled to the first bias output and a second node which is coupled to the second bias output; and

a second diode element comprising a first node coupled to the second node of the first diode element and a second node coupled to the first node of the second capacitive element and the detector output.

14. The detection circuit of claim 13, wherein the second diode is coupled to at least one of the first and the second bias outputs via a resistive element.

15. The detection circuit of claim 13, wherein at least one of the first and the second diode elements comprises a transistor.

16. The detection circuit of claim 13, wherein the bias circuit comprises a voltage source configured to provide the first bias voltage which is controllable depending on a detection value stored in the second capacitive element.

17. The detection circuit of claim 13, wherein the second capacitive element comprises a current source or a resistive element, respectively connected in parallel with a capacitor.

18. A detection method, comprising:

generating a first bias voltage and a second bias voltage;

deriving a first intermediate signal as a function of the first bias voltage and a radio frequency signal;

deriving a second intermediate signal by rectifying the first intermediate signal depending on the second bias voltage and an instantaneous value of the first intermediate signal;

storing a detection value corresponding to an amplitude of the radio frequency signal;

deriving a third intermediate signal by rectifying the second intermediate signal depending on the stored detection value and an instantaneous value of the second intermediate signal; and

adjusting the stored detection value depending on the third intermediate signal.

19. The method of claim 18, wherein adjusting the stored detection value comprises charging a capacitive element depending on the third intermediate signal.

20. The method of claim 19, wherein adjusting the stored detection value comprises discharging the capacitive element depending on the third intermediate signal.

21. The method of claim 18, wherein deriving the second intermediate signal comprises adapting the second bias voltage depending on the second intermediate signal.

22. A detection method performed in an amplifier arrangement, wherein the amplifier arrangement comprises an amplifier circuit and a detection circuit, the detection circuit comprising a bias circuit configured to generate a first bias voltage and a second bias voltage, a series connection of a first diode element and a second diode element, the series connection receiving the first bias voltage and an amplified radio frequency signal at a first tap, receiving the second bias voltage at a connection node of the first and the second diode element and providing a detection value at a second tap to be stored in a capacitive element, the method comprising:

generating the amplified radio frequency signal using the amplifier circuit as a function of a radio frequency signal; and

deriving the detection value corresponding to an amplitude of the amplified radio frequency signal using the detection circuit.