Dim row suppression system and method for active pixel sensor arrays

• US 20080117317A1
• Filed: 11/17/2006
• Published: 05/22/2008
• Est. Priority Date: 11/17/2006
• Status: Abandoned Application

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Mentzer, Ray Alan
• Application Number:
  US11/601,346
• Publication Number:
  US 20080117317A1
• Time in Patent Office: Days
• US Class Current: 348/245
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An active pixel sensor array includes an imaging sensor subarray, a first reference subarray positioned on a first side of the imaging sensor subarray. The first reference subarray includes a first reference column line. A second reference subarray is positioned on a second side of the imaging subarray. The second reference subarray includes a second reference column line that is electrically coupled to the first reference column line to generate a common reference signal from the first and second reference subarrays. The active pixel sensor array may be a CMOS image sensor and each reference subarray may include a plurality of column lines associated with a plurality of columns of pixels.

Claims

1. An active pixel sensor array, comprising:

an imaging sensor subarray;

a first reference subarray positioned on a first side of the imaging sensor subarray, the first reference subarray including a first reference column line; and

a second reference subarray positioned on a second side of the imaging subarray, the second reference subarray including a second reference column line that is electrically coupled to the first reference column line to generate a common reference signal from the first and second reference subarrays.

2. The active pixel sensor array of claim 1 wherein each of the first and second reference subarrays includes a plurality of rows of pixels and a plurality of columns of pixels, each column of pixels including an associated column line with the column lines of first and second reference subarrays being electrically interconnected.

3. The active pixel sensor array of claim 1 wherein each subarray includes a plurality of pixels arranged in rows and columns.

4. The active pixel sensor array of claim 3 wherein the pixels contained in respective rows of the subarrays are coupled to corresponding row lines, each row line being adapted to receive row controls signals that include a reset signal and a row activation signal.

5. The active pixel sensor array of claim 3 wherein each pixel comprises a 3T pixel including a reset transistor, an access transistor, and a source follower transistor.

6. The active pixel sensor array of claim 1 wherein each of the reference subarrays further includes a plurality of pixels that are covered by at least one metal layer and at least one color filter.

7. An electronic system, comprising:

processor circuitry;

at least one input device coupled to the processor circuitry;

at least one storage device coupled to the processor circuitry;

at least one output device coupled to the processor circuitry; and

at least one active pixel sensor array coupled to the processor circuitry, the active pixel sensor array including

an imaging sensor subarray;

a first reference subarray positioned on a first side of the imaging sensor subarray, the first reference subarray including first reference column lines; and

a second reference subarray positioned on a second side of the imaging subarray, the second reference subarray including second reference column lines that are electrically coupled to the first reference column lines to generate a common reference signal from the first and second reference subarrays.

8. The electronic system of claim 7 wherein the processor circuitry comprises circuitry operable to cause the system to function as at least one of a digital still camera, cellular telephone, and a digital video camera.

9. The electronic system of claim 7 wherein at least one of the input devices comprises a numeric keypad.

10. The electronic system of claim 7 wherein at least one of the output devices comprises a visual display.

11. The electronic system of claim 7 wherein each of the first and second reference subarrays includes a plurality of column lines, with the column lines of first and second reference subarrays being electrically interconnected to electrically couple the second reference subarray to the first reference subarray.

12. The electronic system of claim 11 wherein each reference subarray further includes a plurality of pixels arranged in rows and columns.

13. The electronic system of claim 12 wherein each pixel comprises a 3T pixel including a reset transistor, an access transistor, and a source follower transistor.

14. The electronic system of claim 7 wherein each of the reference subarrays further includes a plurality of pixels that are covered by at least one metal layer and at least one color filter.

15. A method of reading data out of an active pixel sensor array including a plurality of pixels, the method comprising:

generating a first reference signal from a first group of pixels in the array;

generating a second reference signal from a second group of pixels in the array;

combining the first and second reference signals to generate a final reference signal;

generating an imaging signal for each pixel in a third group of pixels in the array; and

generating a pixel output signal for each pixel in the third group of pixels from the from the corresponding imaging signal and the final reference signal.

16. The method of claim 15 wherein combining first and second reference signals comprises coupling column lines of the first and second groups of pixels together.

17. The method of claim 15 wherein the first and second groups of pixels are located on opposing sides of the third group of pixels.

18. The method of claim 15 wherein generating the pixel output signal for each pixel in the third group comprises a differential signal generated from the difference between the corresponding imaging signal and the final reference signal.

19. The method of claim 15 wherein generating the imaging signal for each pixel in the third group of pixels comprises taking a difference between a reset signal level and an exposed signal level for the corresponding pixel.

20. The method of claim 19 wherein generating the final reference signal includes taking the difference between a reset signal level of the combined first and second reference signals and an exposed signal level of the combined first and second reference signals.