MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL

• US 20080117685A1
• Filed: 11/16/2006
• Published: 05/22/2008
• Est. Priority Date: 11/16/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Syzdek, Ronald J., Chrudimsky, David W., He, Xiaojie
• Granted Patent: US 7,564,716 B2
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

Claims

1. A method comprising:

determining, for a first set of bit cells of a non-volatile memory array, a first read reference level of a plurality of read reference levels; and

storing an indicator of the first read reference level in a non-volatile storage location associated with the first set of bit cells.

2. The method of claim 1, further comprising:

accessing the indicator of the first read reference level in response to a read access operation to the first set of bit cells; and

sensing a value stored at a memory location of the first set of bit cells based on the indicator of the first read reference level, the memory location of the first set of bit cells associated with the read access operation.

3. The method of claim 2, wherein sensing the value comprises:

generating the first read reference level based on the indicator; and

comparing a reference output from the memory location with the first read reference level to determine the value.

4. The method of claim 2, wherein sensing the value stored at the memory location of the first set of bit cells comprises configuring a sense amplifier to sense the value using a read reference substantially equivalent to the first read reference level.

5. The method of claim 4, wherein configuring the sense amplifier to sense the value comprises configuring an adjustable read reference generator to provide the read reference substantially equivalent to the first read reference level to the sense amplifier.

6. The method of claim 1, wherein accessing the indicator comprises accessing the indicator from the non-volatile storage location.

7. The method of claim 1, further comprising:

accessing the indicator of the first read reference level from the non-volatile storage location and storing the accessed indicator at a volatile storage location in response to a reset event; and

wherein accessing the indicator in response to the read access operation comprises accessing the indicator from the volatile storage location in response to the read access operation.

8. The method of claim 1, wherein determining the first read reference level comprises determining the first read reference level at a first time, the method further comprising:

determining, for the first set of bit cells, a second read reference level of a plurality of read reference levels at a second time subsequent to the first time; and

storing an indicator of the second read reference level in the non-volatile storage location associated with the first set of bit cells.

9. The method of claim 8, further comprising:

accessing the indicator of the first read reference level in response to a first read access operation to the first set of bit cells occurring subsequent to the first time and prior to the second time;

sensing a value stored at a first memory location of the first set of bit cells based on the indicator of the first read reference level, the first memory location of the first set of bit cells associated with the first read access operation;

accessing the indicator of the second read reference level in response to a second read access operation to the first set of bit cells occurring subsequent to the second time; and

sensing a value stored at a second memory location of the first set of bit cells based on the indicator of the second read reference level, the second memory location of the first set of bit cells associated with the second read access operation.

10. The method of claim 1, further comprising:

determining, for a second set of bit cells of the non-volatile memory array, a second read reference level of the plurality of read reference levels; and

storing an indicator of the second read reference level in a non-volatile storage location associated with the second set of bit cells.

11. The method of claim 10, further comprising:

accessing the indicator of the first read reference level in response to a first read access operation to the first set of bit cells; and

sensing a value stored at a memory location of the first set of bit cells based on the indicator of the first read reference level, the memory location of the first set of bit cells associated with the first read access operation;

accessing the indicator of the second read reference level in response to a second read access operation to the second set of bit cells; and

sensing a value stored at a memory location of the second set of bit cells based on the indicator of the second read reference level, the memory location of the second set of bit cells associated with the second read access operation.

12. The method of claim 1, wherein determining the first read reference level comprises:

performing an erase operation on a subset of bit cells of the first set of bit cells;

determining each of the subset of bit cells has a select state based on a select read reference in response to performing the erase operation; and

determining the first read reference level based on the select read reference.

13. The method of claim 1, wherein determining the first read reference comprises:

performing a first erase operation on a subset of bit cells of the first set of bit cells;

determining at least one of the subset of bit cells has a first state based on a first read reference in response to performing the first erase operation;

adjusting the first read reference to generate a second read reference;

performing a second erase operation on the subset of bit cells subsequent to adjusting the first read reference;

determining each of the subset of bit cells has a second state based on the second read reference in response to performing the second erase operation;

determining the first read reference level based on the second read reference.

14. A method comprising:

receiving a first read access request to a first memory location of a first set of bit cells of a non-volatile memory array;

accessing a first indicator of a first read reference level from a first non-volatile storage location in response to receiving the first read access request; and

sensing a value stored at the first memory location based on the first indicator.

15. The method of claim 14, further comprising:

adjusting the first indicator to generate a second indicator of a second read reference level;

storing the second indicator at the first non-volatile storage location;

receiving a second read access request to a second memory location of the first set of bit cells;

accessing a second indicator from the first non-volatile storage location in response to receiving the second read access request; and

sensing a value stored at the second memory location based on the second indicator.

16. The method of claim 14, wherein sensing the value stored at the first memory location comprises configuring a sense amplifier to sense the value using a read reference substantially equivalent to the first read reference level represented by the first indicator.

17. The method of claim 16, wherein configuring the sense amplifier to sense the value comprises configuring an adjustable read reference generator to provide the read reference based on the first indicator.

18. The method of claim 14, wherein accessing the first indicator from the first non-volatile storage location comprises:

accessing the first indicator from the first non-volatile storage location and storing the accessed first indicator at a volatile storage location in response to a reset event; and

accessing the first indicator from the volatile storage location in response to the first read access operation.

19. The method of claim 14, further comprising:

receiving a second read access request to a memory location of a second set of bit cells of the non-volatile memory array;

accessing a second indicator of a read reference level from a second non-volatile storage location in response to receiving the second read access request; and

sensing a value stored at the memory location of the second set of bit cells based on the second indicator.

20. A device comprising:

a non-volatile memory array comprising a plurality of sets of bit cells;

a plurality of non-volatile storage locations, each non-volatile storage location associated with a corresponding set of bit cells of the plurality of bit cells; and

a reference configuration module configured to determine a read reference level for each of the plurality of sets of bit cells and store an indicator of the read reference level in a corresponding non-volatile storage location of the plurality of non-volatile storage locations.

21. The device of claim 20, further comprising:

an adjustable read reference module comprising an output to provide an adjustable read reference; and

a sense amplifier module comprising an output to provide a sensed value from a select set of bit cells of the non-volatile memory array based on the adjustable read reference; and

wherein the reference configuration module is configured to control the variable read reference module so as to adjust the adjustable read reference based on an indicator of a read reference level of the select set of bit cells in response to a read access request to a memory location of the select set of bit cells.

22. The device of claim 21, wherein the sense amplifier module comprises:

an input coupleable to the select set of bit cells; and

an input coupled to the output of the read reference module.

23. The device of claim 21, wherein the sense amplifier module comprises:

an input coupled to the output of the read reference module and coupleable to the select set of bit cells the output of the read reference module; and

an input to receive a fixed read reference.

24. The device of claim 20, wherein the bit cells of the non-volatile memory array comprise thin-film storage bit cells.

25. The device of claim 20, wherein the first set of bit cells comprises a sector of the non-volatile memory array.