Monolithic IC and MEMS microfabrication process

• US 20080119000A1
• Filed: 11/20/2006
• Published: 05/22/2008
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Mantis Vision, Ltd.
• Original Assignee: Alces Technology, Inc. (Mantis Vision, Ltd.)
• Inventors: Yeh, Richard, Bloom, David M.
• Granted Patent: US 7,875,484 B2
• Time in Patent Office: Days
• US Class Current: 438/50
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration

Abstract

Monolithic IC/MEMS processes are disclosed in which high-stress silicon nitride is used as a mechanical material while amorphous silicon serves as a sacrificial layer. Electronic circuits and micro-electromechanical devices are built on separate areas of a single wafer. The sequence of IC and MEMS process steps is designed to prevent alteration of partially completed circuits and devices by subsequent high process temperatures.

Claims

1. A microfabrication process comprising the steps of:

processing a silicon wafer according to an IC front-end process section;

processing the wafer according to a MEMS front-end process section;

processing the wafer according to an IC back-end process section; and

,

processing the wafer according to a MEMS back-end process section;

wherein,

the MEMS front-end process section includes;

depositing an amorphous silicon MEMS sacrificial layer; and

, depositing a silicon nitride MEMS structural layer.

2. The microfabrication process of claim 1 wherein the IC front-end and IC back-end process sections comprise CMOS front-end and CMOS back-end processes, respectively.

3. The microfabrication process of claim 2 wherein each successive process section includes only process steps having process temperatures less than the greatest process temperature encountered in the previous process section.

4. The microfabrication process of claim 3 wherein electronic and micro-electromechanical devices are fabricated in separate areas of the wafer.

5. The microfabrication process of claim 2 wherein the CMOS front-end processes include process steps having process temperatures greater than about 800°

C.

6. The microfabrication process of claim 5 wherein the CMOS front-end processes includes process steps of oxidation, ion implantation, dopant drive-in and annealing, and gate polysilicon deposition.

7. The microfabrication process of claim 2 wherein the MEMS front-end process section includes only process steps having process temperatures less than about 800°

C.

8. The microfabrication process of claim 7 wherein the MEMS front-end process section includes process steps of deposition of a sacrificial layer, a mechanical layer and an encapsulation layer.

9. The microfabrication process of claim 2 wherein the CMOS back-end processes include only process steps having process temperatures less than about 450°

C.

10. The microfabrication process of claim 9 wherein the CMOS back-end processes section include process steps of deposition of interlayer dielectrics, metal layers and passivation.

11. The microfabrication process of claim 2 wherein the MEMS back-end process section includes only process steps having process temperatures less than about 250°

C.

12. The microfabrication process of claim 11 wherein the MEMS back-end process section includes process steps of removing sacrificial layers, final metallization and packaging.

13. The microfabrication process of claim 12 wherein metallization is accomplished by evaporation through a shadow mask.

14. A microfabricated device made by the process of claim 1, the device having electronic circuits and micro-electromechanical devices integrated on a single wafer.

15. The microfabricated device of claim 14, wherein the MEMS mechanical devices comprise high-stress silicon nitride.

16. A microfabrication process comprising the steps of:

processing a silicon wafer according to a MEMS front-end process section;

processing the wafer according to a complete IC process section; and

,

processing the wafer according to a MEMS back-end process section;

wherein,

the MEMS front-end process section includes;

isolation oxidation;

depositing an amorphous silicon MEMS sacrificial layer; and

, depositing a silicon nitride MEMS structural layer.

17. The microfabrication process of claim 16 wherein the IC process section comprises CMOS processing steps.

18. The microfabrication process of claim 17 wherein electronic and micro-electromechanical devices are fabricated in separate areas of the wafer.

19. The microfabrication process of claim 16 wherein the MEMS front-end process section includes MEMS LOCOS processing.

20. A microfabricated device made by the process of claim 16, the device having electronic circuits and micro-electromechanical devices integrated on a single wafer.

21. The microfabricated device of claim 20, wherein the MEMS mechanical devices comprise high-stress silicon nitride.