Transaction co-validation across abstraction layers

• US 20080120085A1
• Filed: 01/12/2007
• Published: 05/22/2008
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Alexanian, Herve Jacques, Chou, Chien Chun
• Granted Patent: US 8,868,397 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method, apparatus, and system in which a modeling tool made up of a testbench executable program validates behavior of one or more sub-components of an electronic system design modeled as one or more executable behavioral models and a transactor translates a behavior of the sub-components between one or more different levels of abstraction derived from a same design.

Claims

1. A modeling tool, comprising:

a testbench executable program to validate behavior of one or more sub-components of an electronic system design modeled as one or more executable behavioral models;

a transactor to translate a behavior of the one or more sub-components between the one or more different levels of abstraction derived from the same electronic system design based upon an applied sequence of test patterns and expected test results from a same instance of the testbench executable program; and

a transactional-testbench interface to allow the transactor to access the applied sequences generated by the testbench executable program, wherein the testbench executable program, the transactor, and the transactional-testbench interface are to be stored and executed on a machine readable storage medium.

2. The modeling tool of claim 1, wherein the testbench executable program includes code scripted as a sequence of test patterns and expected test results used to validate the behavior of the sub-components and a same instance of the testbench executable program provides the sequence of test patterns and expected test results to validate the modeled sub-components at the different levels of abstraction.

3. The modeling tool of claim 1, further comprising:

a timing module to generate correlation measurements of timing approximation between the different levels of abstraction of the sub-components.

4. The modeling tool of claim 1, further comprising:

a functional correlation module to establish a functional correlation between the different levels of abstraction of a first sub-component having the common testbench executable program applied to all levels of abstraction of the sub-component.

5. The modeling tool of claim 1, wherein the transactor includes a port interface containing code to interface with the testbench executable program and a channel to store information passed between the transactor and the port interface, wherein the transactor to convert stimulus requests sent from the testbench executable program from a first level of abstraction to a level of abstraction that the sub-components of the design under verification possess, and to convert stimulus responses sent from the sub-components of the design under verification from the level of abstraction that the design under verification possesses to the first level of abstraction of the testbench executable program.

6. The modeling tool of claim 5, wherein the port interface, the channel and the transactor are coded as three separate modules.

7. The modeling tool of claim 1, wherein the testbench executable program determines one or more behavioral descriptions of the sub-components by applying a common stimulus to all different levels of abstraction of the sub-components.

8. The modeling tool of claim 7, further comprising:

one or more monitor components to record the behavioral descriptions of the sub-components between two or more different levels of abstraction from the same design having the common testbench executable program applied to all levels of abstraction, and

a correlation component to correlate the behavioral descriptions of the sub-components between two or more different levels of abstraction from the same design.

9. The modeling tool of claim 1, further comprising:

a standard configuration application programming interface coded in a derivative of C language to receive parameters of the modeled sub-components.

10. The modeling tool of claim 1, wherein the testbench executable program includes a first internal buffer of transaction data structures for each port of the electronic system design.

11. A method, comprising:

correlating a behavior of one or more sub-components of an electronic system design, modeled as one or more executable behavioral models, to one or more different levels of abstraction derived from a same design; and

validating the behavior of the sub-components with a same instance of a testbench executable program.

12. The method of claim 11, wherein the instance of the testbench executable program defines a transaction data structure of the electronic system design, produces one or more sequences of test patterns and expected test results, and communicates the sequences of test patterns and expected test results at a first level of abstraction to the modeled sub-components of the electronic system design, at a second level of abstraction via a transactional-testbench interface.

13. The method of claim 11, further comprising:

obtaining a first transaction from the testbench executable program and converting the first transaction from a first level of abstraction to a second level of abstraction.

14. The method of claim 11, wherein the correlating further comprises:

recording a first timing data derived from a first simulation of the sub-components represented at a first abstraction level;

recording a second timing data derived from a second simulation of the sub-components represented at a second abstraction level; and

comparing the first timing data to the second timing data for one or more stimulus generated from the testbench executable program.

15. The method of claim 14, further comprising:

verifying end to end checks concurrently with comparing timing results from the sub-components of the electronic system design under verification at different levels of abstraction.

16. The method of claim 11, wherein the correlating further comprises:

recording a first set of functional results derived from a first simulation of the sub-components represented at a first abstraction level;

recording a second set of function results derived from a second simulation of the sub-components represented at a second abstraction level; and

comparing the first set of functional results to the second set of functional results when a stimulus from the testbench executable program is generated.

17. The method of claim 14, wherein the testbench executable program assigns a unique identifier to a first transaction generated as part of the stimulus from the testbench executable program.

18. The method of claim 17, further comprising:

using the unique identifier for the first transaction to match functional results between different levels of abstraction of the sub-components of the electronic system design under verification.

19. The method of claim 11, further comprising:

reading a first data set, containing a response at a first level of abstraction to a request sent by the testbench executable program, from a first transaction monitor placed on a first test channel;

reading a second data set, containing a response at a second level of abstraction obtained for a request sent by the testbench executable program, from a second transaction monitor placed on a second test channel; and

determining an equivalence of the responses found in the first data set and the second data set for each level of abstraction of the sub-components.

20. A computing system, comprising:

a processor component, the processor component to execute instructions; and

a testbench executable program which when executed by the processor to generate and apply a sequence of test patterns and expected test results to sub-components of a design of an electronic system under verification at two or more levels of abstraction, and

a transactor to translate a behavior of the one or more sub-components between the one or more different levels of abstraction derived from the same electronic system design based upon the applied sequence of test patterns and expected test results from a same instance of the testbench executable program; and

a transactional-testbench interface to allow the transactor to access and exploit the sequences generated by the testbench executable program.

21. The computing system of claim 20, wherein the testbench executable program to send out one or more transactions at a transaction level of abstraction to a port interface, the port interface to receive the testbench transactions and send them to a first channel, the first channel to store the transactions in a buffer until a first instance of a transactor is ready to receive the transactions, and the first instance of the transactor to convert the transactions to the level of abstraction of the sub-components of the design under verification.

22. The computing system of claim 21, further comprising:

a correlation component to correlate a cycle accuracy of the sub-components between two or more different levels of abstraction from the same design