Address translation performance in virtualized environments

• US 20080120487A1
• Filed: 11/21/2006
• Published: 05/22/2008
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Saripalli, Ramakrishna
• Granted Patent: US 7,707,383 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system

Abstract

Methods and apparatus to improve address translation performance in virtualized environments are described. In one embodiment, a switching logic may translate a virtual address of a memory access request (e.g., transmitted by a transmitting agent and directed to a receiving agent) into a corresponding physical address. Other embodiments are also disclosed.

Claims

1. An apparatus comprising:

a first logic to decode a memory access request, from a peripheral device to an interface device, to determine whether a virtual address is identified by the memory access request; and

a second logic to translate the virtual address into a physical address based on data stored in a cache.

2. The apparatus of claim 1, wherein the interface device comprises a third logic to transmit an address translation completion packet, the address translation completion packet to comprise address translation data corresponding to a request by the peripheral device to translate one or more virtual addresses into one or more corresponding physical addresses.

3. The apparatus of claim 2, further comprising a fourth logic to update a corresponding entry of the cache in accordance with the address translation data of the address translation completion packet.

4. The apparatus of claim 1, wherein the interface device comprises a third logic to generate an address translation invalidation request.

5. The apparatus of claim 4, further comprising a fourth logic to invalidate a corresponding entry of the cache in response to the address translation invalidation request.

6. The apparatus of claim 1, further comprising a third logic to replace the virtual address in the memory access request with the physical address to provide an updated memory access request.

7. The apparatus of claim 6, wherein the third logic is to transmit the updated memory access request to the interface device.

8. The apparatus of claim 1, further comprising a memory to store data in an entry that corresponds to the physical address.

9. The apparatus of claim 1, wherein one or more of the first logic, the second logic, one or more processor cores, or the cache are on a same integrated circuit die.

10. The apparatus of claim 1, wherein one or more of the first logic, the second logic, the interface device, or the cache are on a same integrated circuit die.

11. A method comprising:

receiving a memory access request transmitted from a peripheral device to an interface device;

determining whether the memory access request comprises a virtual address; and

translating the virtual address into a corresponding physical address.

12. The method of claim 11, further comprising replacing the virtual address in the memory access request with the physical address to provide an updated memory access request.

13. The method of claim 12, further comprising transmitting the updated memory access request to the interface device.

14. The method of claim 11, further comprising updating a cache based on one or more packets transmitted from the interface device to the device.

15. The method of claim 11, wherein the determining comprises decoding the memory access request.

16. The method of claim 11, wherein translating the virtual address into the corresponding physical address comprises accessing a cache.

17. A system comprising:

a storage unit to store a virtual address and a physical address corresponding to the virtual address; and

a switching logic to receive a memory access request from an input/output (I/O) device and directed to a chipset to access a location within a system memory identified by a virtual address, the switching logic to translate the virtual address into a corresponding physical address and to transmit an updated memory access request with the physical address to the chipset.

18. The system of claim 17, wherein the switching logic decodes the memory access request to determine an existence of the virtual address.

19. The system of claim 17, wherein the storage unit comprises a cache.

20. The system of claim 19, further comprising a cache update logic to update one or more entries of the cache in accordance with one or more packets transmitted by the chipset.

21. The system of claim 17, wherein the memory access request comprises one or more of a memory read request or a memory write request.

22. The system of claim 17, wherein the chipset comprise a virtualization logic to translate virtual addresses into physical addresses.

23. The system of claim 17, wherein the switching logic is coupled to the I/O device and the chipset via a peripheral component interconnect.

24. The system of claim 17, further comprising an audio device coupled to the switching logic.