AUTOMATED CONFIGURATION OF A PROCESSING SYSTEM USING DECOUPLED MEMORY ACCESS AND COMPUTATION

• US 20080120497A1
• Filed: 11/20/2006
• Published: 05/22/2008
• Est. Priority Date: 11/20/2006
• Status: Abandoned Application

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bellas, Nikos, Dwyer, Malcolm R., Chai, Sek M., Linzmeier, Daniel A.
• Application Number:
  US11/561,486
• Publication Number:
  US 20080120497A1
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A method and system for automatic configuration of processor hardware from an application program that has stream descriptor definitions, descriptive of memory access locations, data access thread definitions having a stream descriptor and a data channel source or sink as parameters, and computation thread definitions having a function pointer, a data channel source and a data channel sink as parameters. The application program is compiled to produce a description of the data flow between the threads as specified in the application program. The hardware is configured to have streaming memory interface devices operable to access a memory in accordance with the stream descriptor definitions, data path devices operable to process data in accordance with the computation thread definitions and data channels operable to connect the data path devices and streaming memory interface devices in accordance with the description of the data flow.

Claims

1. A method for automatic configuration of processing hardware for an application defined by a plurality of programming instructions of a high level language that include at least one stream description, descriptive of data access locations, at least one data access thread definition, and at least one computation thread definition, the method comprising:

compiling the plurality of programming instructions of the application to produce a description of a data flow between the at least one data access thread and the at least one computational thread;

configuring at least one stream access device operable to access data in accordance with the at least one stream description;

configuring, in the processing hardware, at least one data path device operable to process data in accordance with the at least one computation thread definition; and

configuring, in the processing hardware, one or more data channels operable to connect the at least one data path device and the at least one stream access device in accordance with the description of the data flow.

2. A method in accordance with claim 1, wherein configuring at least one stream access device comprises configuring, in the processing hardware, at least one streaming memory interface device.

3. A method in accordance with claim 1, wherein the data access thread definition has a stream description and one of a data channel source and a data channel sink as parameters, and wherein the computation thread definition has a function pointer, a data channel source and a data channel sink as parameters.

4. A method in accordance with claim 1, wherein compiling the plurality of programming instructions includes:

generating executable code for a scalar processor of the processing hardware; and

outputting the executable code to a computer readable medium.

5. A method in accordance with claim 1, wherein compiling the plurality of programming instructions comprises:

generating a control flow graph (CFG) including references to the at least one data access thread and the at least one computation thread;

generating a symbol table with references to the at least one data access thread, the at least one computation thread and the at least one stream descriptor.

6. A method in accordance with claim 1, wherein configuring a data path device of the at least one data path device comprises:

generating a data flow graph (DFG) for a computation thread referenced in the CFG and symbol table, the computation defined by a function associated with the function pointer parameter of the computation thread;

generating a register transfer level (RTL) description of the DFG;

configuring the data path device in the processing hardware in accordance with the RTL description; and

outputting executable processor code associated with the DFG to a computer readable medium.

7. A method in accordance with claim 1, wherein configuring one or more data channels in the processor hardware comprises:

generating a register transfer level (RTL) description of a data channel in accordance with the description of the data flow; and

configuring the data path device in the processing hardware in accordance with the RTL description.

8. A method in accordance with claim 1, wherein a data channel of the one or more data channels is selected from the group consisting of a bus connection, a tile buffer and a FIFO buffer.

9. A method in accordance with claim 1, wherein the processing hardware comprises a field programmable gate array (FPGA).

10. A method in accordance with claim 1, wherein a stream description of the at least one stream description includes at least one of a starting address, a STRIDE value, a SPAN value, a SKIP value, and a TYPE value.

11. A system for automatic configuration of processing hardware, the system comprising:

an application program interface (API) tool comprising;

a data access thread class;

a computation thread class

a stream descriptor data type;

the API tool operable to enable a programmer to produce an application program that defines data access threads, computation threads, stream descriptors and data movement between the threads;

a compiler operable to compile the application program to produce a description of data flow referencing the data access threads, the computation threads and stream descriptors of the application program;

a hardware description generator operable to generate a hardware description and executable code dependent upon the description of the data flow; and

a configuration element operable to configure the processing hardware in accordance with the hardware description.

12. A system in accordance with claim 11, wherein the stream descriptors include at least one of a starting address, a STRIDE value, a SPAN value, a SKIP value, and a TYPE value.

13. A system in accordance with claim 11, wherein the hardware description comprises:

a description of a streaming memory interface device dependent upon a stream descriptor of the application program;

a description of a data path device dependent upon a computation thread of the application program; and

one or more data channels dependent upon data movement between the threads of the application program.

14. A system in accordance with claim 11, wherein the hardware description comprises a register transfer level (RTL) description stored in a computer readable medium.

15. A system in accordance with claim 11, wherein the configuration element comprises a device programmer.

16. A system in accordance with claim 11, wherein the description of the data flow comprising a control flow graph (CFG) and a symbol table and wherein the hardware description generator is operable to generate a data flow graph (DFG) for a computation thread referenced in the CFG and symbol table, wherein the DFG describes a function associated with the computation thread.

17. A system in accordance with claim 11, wherein the configuration element comprises a memory write thread class and a memory reader thread class.

18. A method for automatic configuration of a processing system for execution of an application, the method comprising:

generating a plurality of programming instructions of a high level language to define the application, the plurality of programming instructions including

at least one data access thread definition dependent upon a software class template for a data access thread, each data access thread having a stream descriptor and one of a data channel source and a data channel sink as parameters;

at least one computation thread definitions dependent upon a software class template for a computation thread;

each computation thread definition having a function pointer, a data channel source and a data channel sink as parameters; and

at least one stream descriptor definitions, descriptive of memory access locations,

compiling the plurality of programming instructions of the application to produce a description of a data flow between the at least one data access thread and the at least one computational thread;

configuring at least one stream access module operable to access a memory in accordance with the at least one stream descriptor definition;

configuring, in the processing system, at least one data path module operable to process data in accordance with the at least one computation thread definition; and

configuring, in the processing system, one or more data channels operable to connect the at least one data path module and the at least one streaming memory interface module accordance with the description of the data flow.

19. A method in accordance with claim 18, wherein generating a plurality of programming instructions of a high level language comprises a programmer using a software tool that provides an application programming interface (API) to the programmer.

20. A method in accordance with claim 19, wherein generating a plurality of programming instructions of a high level language further comprises the programmer using software methods for data movement provided by the software tool.

21. A method in accordance with claim 18, wherein the processing system comprises a general purpose programmable processor.

22. A method in accordance with claim 18, wherein the processing system comprises a processor having configurable hardware.

23. A method in accordance with claim 18, wherein the software class template for a data access thread and the software template for a computation thread are C++ class templates.

24. A method in accordance with claim 18, wherein compiling the plurality of programming instructions comprises:

generating a control flow graph (CFG) including references to the at least one data access thread and the at least one computation thread;

generating a symbol table with references to the at least one data access thread, the at least one computation thread and the at least one stream descriptor