Security features in interconnect centric architectures

• US 20080120520A1
• Filed: 11/17/2006
• Published: 05/22/2008
• Est. Priority Date: 11/17/2006
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Eriksson, Timo
• Granted Patent: US 7,962,786 B2
• Time in Patent Office: Days
• US Class Current: 714/25
• CPC Class Codes: G06F 21/81 by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

A method comprising: detecting a sub-system to be controlled in a reduced resource mode in a device having an interconnecting system architecture; sending a resource reducing request to an interconnect node of the sub-system, the interconnect node belonging to a first power/clock signal domain; and reducing resources of processing elements of the sub-system belonging to a second power/clock signal domain.

Claims

1. A method comprising:

detecting a sub-system to be controlled in a reduced resource mode in a device having an interconnecting system architecture;

sending a resource reducing request to an interconnect node of the sub-system, said interconnect node belonging to a first power/clock signal domain; and

reducing resources of processing elements of the sub-system belonging to a second power/clock signal domain.

2. The method according to claim 1 further comprising:

sending a dedicated control signal from the interconnect node of the sub-system to a controller of the sub-system to be controlled in the reduced resource mode, for controlling the resource reducing of the processing elements belonging to the second power/clock signal domain, said control signal enabling the resource reducing of the processing elements.

3. The method according to claim 1, wherein

the sub-system to be controlled in the reduced resource mode is a malfunctioning sub-system or a sub-system having lost its integrity.

4. The method according to claim 3, further comprising:

detecting the loss of integrity of a sub-system on the basis of an integrity check number or an alarm received from the sub-system.

5. The method according to claim 3, further comprising:

detecting a malfunctioning sub-system on the basis of power usage and/or interconnect misbehaviour.

6. The method according to claim 3, further comprising:

checking, in response to the malfunctioning or the loss of integrity being recovered, validity of a boot-up image of the malfunctioning or the integrity failing sub-system;

sending a resource reducing removal request to the interconnect node of the malfunctioning or the integrity failing sub-system;

disabling the dedicated control signal to remove the reduced resource mode of the sub-system; and

activating the power and clock signals for the processing elements belonging to the second power/clock signal domain.

7. The method according to claim 1, wherein the resource reducing is carried out according to at least one of the following processes:

shutting down the processing elements of the sub-system belonging to the second power/clock signal domain;

reducing the maximum power available for the processing elements of the sub-system belonging to the second power/clock signal domain;

reducing the interconnect throughput available for the processing elements of the sub-system belonging to the second power/clock signal domain.

8. An apparatus comprising:

a managing sub-system comprising a security manager for monitoring the operation of the apparatus having an interconnecting system architecture;

one or more non-managing subsystems, said non-managing sub-systems comprising a first power/clock signal domain including an interconnect node and at least a second power/clock signal domain including one or more processing elements of the sub-system;

wherein the security manager is arranged to detect a sub-system to be controlled in a reduced resource mode and send a resource reducing request to an interconnect node of the sub-system, and

the interconnect node of the sub-system to be controlled in a reduced resource mode is arranged to reduce the resources of the processing elements belonging to the second power/clock signal domain.

9. The apparatus according to claim 8, the non-managing sub-systems further comprising:

a controller for controlling the resource reducing of the processing elements belonging to the second power/clock signal domain;

wherein

the interconnect node of the sub-system to be controlled in a reduced resource mode is arranged to send a dedicated control signal to said controller to enable the resource reducing of the processing elements.

10. The apparatus according to claim 9, wherein the controller comprises a local clock generator and a power generator.

11. The apparatus according to claim 9, further comprising an external clock generator and power generator;

wherein the controller comprises a local switch.

12. The apparatus according to claim 8, wherein the processing elements belonging to the second power/clock signal domain comprise at least one of the following:

on-chip processing elements and/or memories;

off-chip processing elements, memories and/or peripherals.

13. The apparatus according to claim 8, wherein the sub-system to be controlled in the reduced resource mode is a malfunctioning sub-system or a sub-system having lost its integrity.

14. The apparatus according to claim 13, wherein the security manager is arranged to detect the loss of integrity of a sub-system on the basis of an integrity check number or an alarm received from the sub-system.

15. The apparatus according to claim 13, wherein the security manager is arranged to detect a malfunctioning sub-system on the basis of power usage and/or interconnect misbehaviour.

16. The apparatus according to claim 13, wherein

the security manager is arranged, in response to the malfunctioning or the loss of integrity being recovered, to check validity of a boot-up image of the malfunctioning or the integrity failing sub-system and to send a resource reducing removal request to the interconnect node of the malfunctioning or the integrity failing sub-system;

and

the interconnect node of the malfunctioning sub-system is arranged to disable the dedicated control signal to remove the reduced resource mode and to activate the power and clock signals for the processing elements belonging to the second power/clock signal domain.

17. The apparatus according to claim 8, wherein the resource reducing mode includes at least one of the following processes:

shutting down the processing elements of the sub-system belonging to the second power/clock signal domain;

reducing the maximum power available for the processing elements of the sub-system belonging to the second power/clock signal domain;

reducing the interconnect throughput available for the processing elements of the sub-system belonging to the second power/clock signal domain.

18. A module, attachable to a data processing device, comprising a managing sub-system for an interconnecting centric system architecture, said managing sub-system comprising a security manager for monitoring the operation of an apparatus having an interconnecting centric system architecture;

wherein the security manager is arranged to detect a sub-system to be controlled in a reduced resource mode and send a resource reducing request to an interconnect node of the sub-system.

19. The module according to claim 18, wherein:

the module is implemented as a chipset.

20. A module, attachable to a data processing device, comprising a non-managing subsystem for an interconnecting centric system architecture, said non-managing sub-system comprising a first power/clock signal domain including an interconnect node and at least a second power/clock signal domain including one or more processing elements of the sub-system;

wherein the interconnect node of the sub-system is arranged to receive a resource reducing request and to control the processing elements belonging to the second power/clock signal domain in a reduced resource mode.

21. The module according to claim 20, wherein:

the module is implemented as a chipset.

22. An apparatus comprising:

a managing sub-system comprising means for monitoring the operation of the apparatus having an interconnecting system architecture;

one or more non-managing subsystems, said non-managing sub-systems comprising a first power/clock signal domain including an interconnect node and at least a second power/clock signal domain including one or more processing elements of the sub-system;

wherein the means for monitoring is arranged for detecting a sub-system to be controlled in a reduced resource mode and for sending a resource reducing request to an interconnect node of the sub-system, and

the interconnect node of the sub-system to be controlled in a reduced resource mode is arranged to reduce the resources of the processing elements belonging to the second power/clock signal domain.