Density-Based Layer Filler for Integrated Circuit Design

• US 20080120586A1
• Filed: 11/21/2006
• Published: 05/22/2008
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hoerold, Stephan
• Granted Patent: US 7,565,638 B2
• Time in Patent Office: Days
• US Class Current: 716/9
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may identify open areas on a given design layer in which one or more minimum density rules are not met and may insert dummy shapes only in those identified areas. The dummy shapes may be constructed so as not to violate one or more other design rules. The density-based layer filler may access a configuration file comprising layer density rules and other design rules and may generate a run deck dependent on the contents of the configuration file. The density-based layer filler may be applied iteratively to a design in checking windows of various sizes according to multiple window sizes and step values specified in the configuration file. The dummy shapes may be electrically connected to an existing ground wire after insertion.

Claims

1. A computer implemented method, comprising:

accessing a configuration file, wherein the configuration file comprises;

a minimum density design rule for a design layer of an integrated circuit design layout, wherein the design layer comprises an encoded representation of a photomask to be used in fabrication of the integrated circuit; and

an identifier specifying an area of the design layout on which to operate;

generating a run deck dependent on the configuration file, wherein the run deck comprises program instructions executable to perform a density-based layer filling operation on the area of the design layout specified by the identifier;

executing the program instructions comprised in the run deck to perform the density-based layer filling operation;

wherein the density-based layer filling operation comprises;

identifying a portion of the specified area of the design layout in which the minimum density design rule for the design layer is not met;

constructing one or more dummy shapes to be added on the design layer; and

inserting the one or more dummy shapes into the design layout only in the identified portion of the specified area;

wherein inserting the one or more dummy shapes results in the minimum density design rule for the design layer being met in the identified portion of the specified area.

2. The method of claim 1, further comprising:

determining if said inserting the one or more dummy shapes into the design layout results in the design layout violating a maximum density design rule for the design layer; and

in response to determining that said inserting the one or more dummy shapes into the design layout results in the design layout violating the maximum density design rule for the layer, removing at least one of the one or more dummy shapes.

3. The method of claim 1, wherein said constructing and said inserting comprise constructing and inserting the one or more dummy shapes such that a maximum density design rule for the design layer is not violated.

4. The method of claim 1, wherein said constructing and said inserting comprise constructing and inserting the one or more dummy shapes such that one or more other design rules involving the design layer are not violated, wherein the one or more other design rules are rules other than layer density rules, and wherein the one or more other design rules are specified in the configuration file.

5. The method of claim 1, further comprising:

for each of the one or more dummy shapes;

identifying a suitable ground wire to which the dummy shape may be interconnected; and

electrically connecting the dummy shape to the ground wire.

6. The method of claim 5, wherein said identifying a suitable ground wire to which the dummy shape may be interconnected comprises locating an intersection between the dummy shape and a ground wire on a nearest metal layer;

and wherein electrically connecting the dummy shape to the ground wire comprises adding a via to the design layout to connect the design layer and the nearest metal layer at the intersection.

7. The method of claim 5, wherein said identifying a suitable ground wire to which the dummy shape may be interconnected comprises locating a ground wire on the design layer in the vicinity of the dummy shape;

and wherein electrically connecting the dummy shape to the ground wire comprises inserting an additional shape on the design layer bridging a space between the dummy shape and the ground wire to electrically connect the dummy shape and the ground wire.

8. The method of claim 1, further comprising:

interconnecting the one or more dummy shapes to each other, wherein interconnecting the one or more dummy shapes comprises inserting one or more additional shapes on the design layer each bridging a space between a pair of dummy shapes to electrically connect the one or more dummy shapes;

identifying a suitable ground wire to which the interconnected dummy shapes may be connected; and

electrically connecting at least one of the interconnected dummy shapes to the ground wire.

9. The method of claim 1, wherein said inserting the one or more dummy shapes into the design layout comprises:

adding a representation of the one or more dummy shapes to a design file comprising layout data corresponding to a dummy layer; and

merging the layout data corresponding to the dummy layer with layout data corresponding to the design layer.

10. The method of claim 1, wherein said inserting the one or more dummy shapes into the design layout comprises adding a representation of the one or more dummy shapes to a design file comprising layout data corresponding to the design layer.

11. The method of claim 1, wherein said identifying a portion of the specified area of the design layout in which the minimum density design rule for the design layer is not met comprises:

iteratively applying a minimum density rule check to successive sections of the specified area defined by a checking window as the checking window is stepped horizontally and vertically across the specified area until the minimum density rule check indicates that the minimum density rule is not met; and

in response to the minimum density rule check indicating that the minimum density rule is not met, identifying the section of the specified area in which the minimum density rule is not met;

wherein horizontal and vertical dimensions of the checking window are specified in the configuration file and are specific to the minimum density rule; and

wherein the checking window is stepped across the specified area according to horizontal and vertical step values comprised in the configuration file and specific to the minimum density rule.

12. The method of claim 1, wherein the design layer is a metal layer.

13. A computer implemented method comprising:

iteratively applying a minimum density rule check for a design layer of an integrated circuit design layout to successive sections of the design layout defined by a checking window as the checking window is stepped horizontally and vertically across the design layout until the minimum density rule check indicates that the minimum density rule is not met; and

in response to the minimum density rule check indicating that the minimum density rule is not met;

identifying the section of the design layout in which the minimum density rule is not met;

constructing one or more dummy shapes to be added on the design layer; and

inserting the one or more dummy shapes into the design layout only in the identified section of the design layout;

wherein said inserting the one or more dummy shapes results in the minimum density design rule for the design layer being met in the identified section of the design layout;

wherein the design layer comprises an encoded representation of a photomask to be used in fabrication of the integrated circuit.

14. The method of claim 13, further comprising:

identifying a section of the design layout in which a second minimum density design rule for a second design layer is not met;

constructing one or more dummy shapes to be added on the second design layer; and

inserting the one or more dummy shapes into the design layout only in the identified section of the design layout in which the second minimum density rule is not met.

15. The method of claim 13, further comprising:

iteratively applying a second minimum density rule check for the design layer to successive sections of the design layout defined by a second checking window as the second checking window is stepped horizontally and vertically across the design layout until the second minimum density rule check indicates that the second minimum density rule is not met; and

in response to the second minimum density rule check indicating that the second minimum density rule is not met;

identifying the section of the design layout in which the second minimum density rule is not met;

constructing one or more dummy shapes to be added on the design layer; and

inserting the one or more dummy shapes into the design layout only in the identified section of the design layout in which the second minimum density rule is not met;

wherein said inserting the one or more dummy shapes results in the second minimum density design rule for the design layer being met in the identified section of the design layout;

wherein the second minimum density rule differs from the minimum density rule in at least one of the following parameters;

a horizontal dimension of the checking window, a vertical dimension of the checking window, a horizontal step value of the checking window, a vertical step value of the checking window, and a minimum density requirement.

16. The method of claim 13, wherein said constructing and said inserting comprise constructing and inserting the one or more dummy shapes such that one or more other design rules involving the design layer are not violated.

17. The method of claim 13, wherein parameters of the minimum density design rule comprise:

a horizontal dimension of the checking window, a vertical dimension of the checking window, a horizontal step value of the checking window, a vertical step value of the checking window, and a minimum density requirement; and

wherein the parameters of the minimum density design rule are specified using one or more of;

a configuration file, a command line option, and a menu selection.

18. A system, comprising:

a processor; and

a memory coupled to the processor;

wherein the memory comprises program instructions executable by the processor to implement;

accessing a configuration file, wherein the configuration file comprises;

a minimum density design rule for a design layer of an integrated circuit design layout, wherein the design layer comprises an encoded representation of a photomask to be used in fabrication of the integrated circuit; and

an identifier specifying an area of the design layout on which to operate;

generating a run deck dependent on the configuration file, wherein the run deck comprises program instructions executable to perform a density-based layer filling operation on the area of the design layout specified by the identifier;

executing the program instructions comprised in the run deck to perform the density-based layer filling operation;

wherein the density-based layer filling operation comprises;

identifying a portion of the specified area of the design layout in which the minimum density design rule for the design layer is not met;

constructing one or more dummy shapes to be added on the design layer; and

inserting the one or more dummy shapes into the design layout only in the identified portion of the specified area;

wherein inserting the one or more dummy shapes results in the minimum density design rule for the design layer being met in the identified portion of the specified area.

19. The system of claim 18, wherein the memory further comprises program instructions executable by the processor to implement:

for each of the one or more dummy shapes;

identifying a suitable ground wire to which the dummy shape may be interconnected; and

electrically connecting the dummy shape to the ground wire.

20. The system of claim 18, wherein to identify a portion of the specified area of the design in which the minimum density design rule for the design layer is not met, the memory further comprises program instructions executable by the processor to implement:

iteratively applying a minimum density rule check to successive sections of the specified area defined by a checking window as the checking window is stepped horizontally and vertically across the specified area until the minimum density rule check indicates that the minimum density rule is not met; and

in response to the minimum density rule check indicating that the minimum density rule is not met, identifying the section of the specified area in which the minimum density rule is not met;

wherein horizontal and vertical dimensions of the checking window are specified in the configuration file and are specific to the minimum density rule; and

wherein the checking window is stepped across the specified area according to horizontal and vertical step values comprised in the configuration file and specific to the minimum density rule.