SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME

• US 20080121931A1
• Filed: 08/30/2006
• Published: 05/29/2008
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Byeong Y., Chen, Xiaomeng, Nayfeh, Hasan M., Jeng, Shwu-Jen
• Granted Patent: US 8,754,446 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

Claims

1. A structure, comprising:

a gate oxide layer formed on a substrate;

a gate formed on the gate oxide layer;

a material about walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut; and

source and drain regions isolated from the gate by the material.

2. The device according to claim 1, wherein the gate oxide layer comprises high dielectric constant (high-k) material.

3. The device according to claim 1, wherein the source and drain regions comprise epitaxially grown silicon germanium material.

4. The device according to claim 1, wherein the gate oxide layer has a thickness from about 0.5 nm to about 3 nm.

5. The device according to claim 1, wherein the material is a protective barrier layer of silicon nitride forming sidewalls.

6. The device according to claim 1, wherein the material about the walls of the gate is a thickness of less than 10 nm.

7. The device according to claim 1, wherein the device is a PFET device.

8. The device according to claim 1, wherein the source and drain regions are formed under the gate, beyond at least a portion of the undercut.

21. The device according to claim 1, wherein the undercut is formed in the gate oxide layer.

9-20. -20. (canceled)