Transistor and memory cell array

• US 20080121961A1
• Filed: 09/08/2006
• Published: 05/29/2008
• Est. Priority Date: 09/08/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till
• Granted Patent: US 7,956,387 B2
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

Claims

1. An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising:

first and second source/drain regions;

a channel connecting the first and second source/drain region;

a gate groove defined in the top surface of the semiconductor substrate and comprising an upper and a lower groove portion; and

the gate electrode is disposed in the lower groove portion of the gate groove, the upper groove portion being filled with an insulating material, wherein the gate electrode encloses a channel at the top side and two lateral sides of the channel region.

2. The integrated circuit of claim 1, wherein the gate electrode comprises a metal filling in the gate groove.

3. The integrated circuit of claim 2, wherein the gate electrode comprises metal.

4. The integrated circuit of claim 1, wherein the first source/drain region extends to a different depth than the second source/drain region.

5. The integrated circuit of claim 1, wherein the first source/drain region comprises a different doping concentration than the second source/drain region.

6. The integrated circuit of claim 1, wherein the first source/drain region comprises a first doped portion having a higher doping concentration than a second doped portion forming part of the second source/drain region, the second doped portion being disposed at the same height as the first doped portion.

24. The integrated circuit of claim 1, further comprising a buried conductive line, wherein the gate electrode forms a portion of the buried conductive line.

7. An integrated circuit comprising a memory cell array, the memory cell array comprising:

a plurality of memory cells comprising respective storage elements and access transistors;

bitlines extending in a bitline direction;

wordlines extending in a second direction that intersects the bitline direction;

a semiconductor substrate in which the access transistors are formed, the access transistors electrically coupling corresponding storage elements to corresponding bitlines, the access transistors being addressed by the wordlines, the access transistors comprising doped portions arranged adjacent to the substrate surface, a channel region connecting the doped portions, wherein a top surface of each of the wordlines is disposed beneath the top surface of the semiconductor substrate, wherein a part of the wordline encloses the channel region at a top side and two lateral sides of the channel region.

8. The integrated circuit of claim 7, wherein isolation trenches are formed in the semiconductor substrate, thereby defining active areas, the isolation trenches being configured so as to insulate adjacent active areas from each other, wherein the access transistors are formed in the active areas.

9. The integrated circuit of claim 8, wherein the isolation trenches are filled in a lower portion thereof with an insulating material, the word lines being disposed so as to fill an upper portion of the isolation trenches.

10. The integrated circuit of claim 7, wherein plate-like portions enclose the channel at the top side and at two lateral sides thereof, the plate-like portions being formed in the isolation trenches at a position adjacent to the channel region, the plate-like portions being made of a conductive material and being connected with the wordlines.

11. The integrated circuit of claim 10, wherein the plate-like portions are disposed at a position adjacent to the channel only, a center portion of an upper portion of the isolation trenches being filled with an insulating material.

12. The integrated circuit of claim 7, wherein the storage elements comprise storage capacitors formed in the semiconductor substrate.

13. The integrated circuit of claim 7, wherein the storage elements comprise storage capacitors formed above the semiconductor substrate.

14. The integrated circuit of claim 7, wherein the doped portions of each of the access transistors operate as the first and second source/drain regions, the channel region being formed between the first and second source/drain regions, the access transistors further comprising a gate electrode for controlling an electrical current flowing in the channel, the gate electrode forming part of a corresponding wordline.

15. The integrated circuit of claim 14, wherein the gate electrode is disposed in a gate groove extending in the substrate surface between the first and the second source/drain region.

16. The integrated circuit of claim 15, further comprising an insulating material filling the upper portion of the gate groove.

17. A method of forming an integrated circuit comprising a transistor, the method comprising:

forming a gate groove extending in a substrate surface;

forming first and second source/drain regions, the first and the second source/drain regions being adjacent to the substrate surface;

forming a gate conductive material in the gate groove so that a top surface of the gate conductive material is disposed beneath the substrate surface, thereby defining a gate electrode; and

filling an upper groove portion of the gate groove with an insulating material, wherein the gate groove is formed so that a channel portion connecting the first and the second source/drain regions is enclosed on a top side and two lateral sides by the gate electrode.

18. A method of forming an integrated circuit comprising a memory cell array, the method comprising:

forming a plurality of isolation trenches in a semiconductor substrate to delimit a plurality of active areas;

forming transistors in the active areas forming first and second source/drain regions and a channel region disposed between the first and second source/drain regions; and

forming respective gate electrodes of the transistors by;

forming a gate groove in one of the active areas, the gate groove comprising a lower groove portion and an upper groove portion,

defining pockets in isolation trenches at a position adjacent to the gate groove,

filling the pockets and the lower groove portions with a conductive material thereby forming the gate electrode, and

filling the upper groove portion with an insulating material.

19. The method of claim 18, further comprising etching the active area so as to reduce the width of the active area in the channel region, the etching being performed after defining pockets in the isolation trenches.

20. The method of claim 18, wherein forming a gate groove comprises etching the substrate material.

21. The method of claim 20, wherein defining pockets in the isolation trenches comprises etching the insulating material filled in the isolation trenches.

22. The method of claim 21, wherein etching the insulating material filled in the isolation trenches comprises anisotropically etching the insulating material.

23. An integrated circuit comprising a transistor formed in a semiconductor substrate having a top surface, the transistor comprising:

first and second doped regions adjacent to the top surface;

a channel connecting the first and second doped regions;

means for controlling an electrical current flowing in the channel, wherein the means for controlling the electrical current is disposed in a groove, the groove being defined in the top surface of the semiconductor substrate; and

means for confining lateral sides of the channel, part of the means for controlling an electrical current being disposed in the means for confining the channel,

wherein a top surface of the means for controlling the electrical current is disposed beneath the top surface of the semiconductor substrate.