Finned memory cells and the fabrication thereof

• US 20080121970A1
• Filed: 08/31/2006
• Published: 05/29/2008
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,452,766 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.

Claims

1. A method of forming a memory array, comprising:

forming a plurality fins in a substrate that protrude from a substrate;

after forming the plurality fins, isotropically etching the fins to reduce a width of the fins and to round an upper surface of the fins;

forming a first dielectric layer overlying the isotropically etched fins;

forming a first conductive layer overlying the first dielectric layer;

forming a second dielectric layer overlying the first conductive layer; and

forming a second conductive layer overlying the second dielectric layer.

2. The method of claim 1 further comprises removing portions of the first conductive layer from the first dielectric layer before forming the second layer.

3. The method of claim 2, wherein each remaining portion of the second conductive layer that overlies a portion of a fin terminates at a location that coincides with an axis that bisects a width of the fin.

4. The method of claim 2, wherein each remaining portion of the second conductive layer that overlies a portion of a fin extends past a location that coincides with an axis that bisects a width of the fin.

5. The method of claim 1 further comprises forming fins in the second conductive layer that protrude from the second conductive layer before forming the second dielectric layer.

6. The method of claim 5, wherein forming fins in the second conductive layer comprises isotropically etching the second conductive layer.

7. A method of forming a memory array, comprising:

forming a sacrificial layer overlying a semiconductor substrate;

forming a hard mask layer overlying the sacrificial layer;

patterning the hard mask layer for exposing portions of the hard mask layer and underlying portions of the sacrificial layer and the substrate for removal;

forming trenches through the hard mask layer, the sacrificial layer, and into the substrate by removing the exposed portions of the hard mask layer and the underlying portions of the sacrificial layer and of the substrate;

forming spacers on sidewalls of the trenches;

extending the trenches further into the substrate by removing additional substrate material from the trenches after forming the spacers;

forming isolation regions in the trenches by filling the trenches with dielectric material;

after forming the isolation regions, removing the spacers, the sacrificial layer, and the hard mask layer to form a plurality of fins in the substrate that protrude from the substrate so that an isolation region is located between successive fins;

isotropically etching the fins to reduce a width of the fins and to round an upper surface of the fins;

forming a tunnel dielectric layer overlying the isotropically etched fins;

forming a floating gate layer overlying the tunnel dielectric layer;

forming an intergate dielectric layer overlying the floating gate layer; and

forming a control gate layer overlying the intergate dielectric layer.

8. The method of claim 7 further comprises removing portions of the floating gate layer from the tunnel dielectric layer before forming the intergate dielectric layer.

9. The method of claim 7 further comprises forming fins in the floating gate layer that protrude from the floating gate layer before forming the intergate dielectric layer.

10. The method of claim 9 further comprises recessing the isolation regions below upper surfaces of the floating gate layer before forming the fins in the floating gate layer.

11. The method of claim 9, wherein forming fins in the floating gate layer comprises isotropically etching the floating gate layer.

12. The method of claim 7 further comprises recessing the isolation regions below an upper surface of the semiconductor substrate before removing the spacers, the sacrificial layer, and the hard mask layer.

13. A method of forming a memory array, comprising:

forming a sacrificial layer overlying a semiconductor substrate;

forming a hard mask layer overlying the sacrificial layer;

patterning the hard mask layer for exposing portions of the hard mask layer and underlying portions of the sacrificial layer and the substrate for removal;

forming trenches through the hard mask layer, the sacrificial layer, and into the substrate by removing the exposed portions of the hard mask layer and the underlying portions of the sacrificial layer and of the substrate;

forming spacers on sidewalls of the trenches;

extending the trenches further into the substrate by removing additional substrate material from the trenches after forming the spacers;

forming isolation regions in the trenches by filling the trenches with dielectric material;

recessing the isolation regions below an upper surface of the semiconductor substrate;

after recessing the isolation regions, removing the spacers, the sacrificial layer, and the hard mask layer to form a plurality of fins in the substrate that protrude from the substrate so that an isolation region is located between successive fins;

isotropically etching the fins to reduce a width of the fins and to round an upper surface of the fins;

forming a tunnel dielectric layer overlying the isotropically etched fins;

forming a floating gate layer overlying the tunnel dielectric layer;

removing the floating gate layer from portions of the tunnel dielectric layer so as to leave a portions of the tunnel dielectric layer exposed and such that each remaining portion of the floating gate layer overlies a portion of a fin;

forming an intergate dielectric layer overlying the remaining portions of the floating gate layer and the exposed portions of the tunnel dielectric layer; and

forming a control gate layer overlying the intergate dielectric layer.

14. The method of claim 13, wherein each remaining portion of the floating gate layer that overlies a portion of a fin terminates at a location that coincides with an axis that bisects a width of the fin.

15. The method of claim 13, wherein each remaining portion of the floating gate layer that overlies a portion of a fin extends past a location that coincides with an axis that bisects a width of the fin.

16. The method of claim 13, wherein removing the floating gate layer from portions of the tunnel dielectric layer comprises anisotropically etching.

17. The method of claim 13, wherein removing the floating gate layer from portions of the tunnel dielectric layer comprises removing the floating gate layer from portions of the tunnel dielectric layer so that in every other row of the memory array the remaining portions of the floating gate layer face in a first direction and in intervening rows the remaining portions of the floating gate layer face in a second direction opposite the first direction.

18. A method of forming a memory array, comprising:

forming a sacrificial layer overlying a semiconductor substrate;

forming a hard mask layer overlying the sacrificial layer;

patterning the hard mask layer for exposing portions of the hard mask layer and underlying portions of the sacrificial layer and the substrate for removal;

forming trenches through the hard mask layer, the sacrificial layer, and into the substrate by removing the exposed portions of the hard mask layer and the underlying portions of the sacrificial layer and of the substrate;

forming spacers on sidewalls of the trenches;

extending the trenches further into the substrate by removing additional substrate material from the trenches after forming the spacers;

forming isolation regions in the trenches by filling the trenches with dielectric material;

after forming the isolation regions, removing the spacers, the sacrificial layer, and the hard mask layer to form a plurality of fins in the substrate that protrude from the substrate so that an isolation region is located between successive fins;

isotropically etching the fins to reduce a width of the fins and to round an upper surface of the fins;

forming a tunnel dielectric layer overlying the isotropically etched fins;

forming a floating gate layer overlying the tunnel dielectric layer;

recessing the isolation regions below an upper surface of the floating gate layer;

after recessing the isolation regions isotropically etching the floating gate layer to form fins in the floating gate layer that protrude from the floating gate layer and that respectively overlie the fins in the substrate;

forming an intergate dielectric layer overlying the finned floating gate layer; and

forming a control gate layer overlying the intergate dielectric layer.

19. A method of forming a memory array, comprising:

forming a sacrificial layer overlying a semiconductor substrate;

forming a hard mask layer overlying the sacrificial layer;

patterning the hard mask layer for exposing portions of the hard mask layer and underlying portions of the sacrificial layer and the substrate for removal;

forming trenches through the hard mask layer, the sacrificial layer, and into the substrate by removing the exposed portions of the hard mask layer and the underlying portions of the sacrificial layer and of the substrate;

forming spacers on first and second sidewalls of each of the trenches;

removing the spacer formed on the first sidewall of each of the trenches;

extending the trenches further into the substrate by removing additional substrate material from the trenches after removing the spacers from the first sidewalls of the trenches;

forming isolation regions in the trenches by filling the trenches with dielectric material;

after forming the isolation regions, removing the spacers from the second sidewalls of the trenches and removing the sacrificial layer and the hard mask layer to form a plurality of fins in the substrate that protrude from the substrate so that an isolation region is located between successive fins and so that at least one fin is in contact with an isolation region;

forming a tunnel dielectric layer overlying the isotropically etched fins;

forming a floating gate layer overlying the tunnel dielectric layer;

forming an intergate dielectric layer overlying the floating gate layer; and

forming a control gate layer overlying the intergate dielectric layer.

20. A memory array, comprising:

a plurality fins protruding from a substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein each fin comprises an upper surface rounded by isotropic etching.

21. The memory array of claim 20, wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.

22. The memory array of claim 20, wherein each floating gate overlies a portion of its corresponding fin that protrudes from the substrate.

23. The memory array of claim 22, wherein each floating gate that overlies a portion of its corresponding fin that protrudes from the substrate terminates at a location that coincides with an axis that bisects a width of that corresponding fin.

24. The memory array of claim 22, wherein each floating gate that overlies a portion of its corresponding fin that protrudes from the substrate extends past a location that coincides with an axis that bisects a width of that corresponding fin.

25. A memory array, comprising:

a plurality of isolation regions extending into a substrate;

a plurality fins protruding from the substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein an isolation region is located between successive fins; and

wherein at least one fin is in contact with an isolation region.

26. A memory array, comprising:

a plurality fins protruding from a substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.

27. A memory array, comprising:

a substrate;

a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;

a fin protruding from each active region;

a floating gate memory cell formed on each active region, the memory cell comprising;

a tunnel dielectric layer formed on the active region, including the fin of that active region;

a floating gate formed on a portion of the tunnel dielectric layer;

an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and

a control gate layer formed on the intergate dielectric layer.

28. The memory array of claim 27, wherein the portion of the floating gate terminates at a location coinciding with an axis that bisects a width of the fin.

29. The memory array of claim 27, wherein the portion of the floating gate overlies about half of the fin.

30. The memory array of claim 27, wherein the portion of the floating gate extends beyond a location coinciding with an axis that bisects a width of the fin.

31. The memory array of claim 27, wherein the portion of the floating gate overlies more than half of the fin.

32. A memory array, comprising:

a plurality of rows of memory cells, each row comprising;

a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;

a fin protruding from each active region;

a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising;

a tunnel dielectric layer formed on the active region, including the fin of that active region;

a floating gate formed on a portion of the tunnel dielectric layer;

an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and

a control gate layer formed on the intergate dielectric layer;

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.

33. The memory array of claim 32, wherein the portion of each floating gate terminates at a location coinciding with an axis that bisects a width of a corresponding fin.

34. The memory array of claim 32, wherein the portion of each floating gate overlies about half of a corresponding fin.

35. The memory array of claim 32, wherein the portion of each floating gate extends beyond a location coinciding with an axis that bisects a width of a corresponding fin.

36. The memory array of claim 32, wherein the portion of each floating gate overlies more than half of a corresponding fin.

37. A memory device, comprising:

a memory array; and

control circuitry for controlling operations of the memory array;

wherein the memory array comprises;

a plurality fins protruding from a substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein each fin comprises an upper surface rounded by isotropic etching.

38. A memory device, comprising:

a memory array; and

control circuitry for controlling operations of the memory array;

wherein the memory array comprises;

a plurality of isolation regions extending into a substrate;

a plurality fins protruding from the substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein an isolation region is located between successive fins; and

wherein at least one fin is in contact with an isolation region.

39. A memory device, comprising:

a memory array; and

control circuitry for controlling operations of the memory array;

wherein the memory array comprises;

a substrate;

a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;

a fin protruding from each active region;

a floating gate memory cell formed on each active region, the memory cell comprising;

a tunnel dielectric layer formed on the active region, including the fin of that active region;

a floating gate formed on a portion of the tunnel dielectric layer;

an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and

a control gate layer formed on the intergate dielectric layer.

40. A memory device, comprising:

a memory array; and

control circuitry for controlling operations of the memory array;

wherein the memory array comprises;

a plurality fins protruding from a substrate;

a tunnel dielectric layer overlying the fins;

a plurality floating gates overlying the tunnel dielectric layer, wherein the floating gates correspond one-to-one with the fins protruding from the substrate;

an intergate dielectric layer overlying the floating gates; and

a control gate layer overlying the intergate dielectric layer;

wherein each floating gate comprises a fin protruding therefrom, wherein the fin protruding from each floating gate is aligned with the fin protruding from the substrate that corresponds to that floating gate.

41. A memory device, comprising:

a memory array; and

control circuitry for controlling operations of the memory array;

wherein the memory array comprises;

a plurality of rows of memory cells, each row comprising;

a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;

a fin protruding from each active region;

a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising;

a tunnel dielectric layer formed on the active region, including the fin of that active region;

a floating gate formed on a portion of the tunnel dielectric layer;

an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and

a control gate layer formed on the intergate dielectric layer;

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.

42. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises a memory array, comprising;

a plurality of rows of memory cells, each row comprising;

a plurality of isolation regions formed in the substrate and defining a plurality of active regions of the substrate, wherein an isolation region is formed between a pair of successive active regions;

a fin protruding from each active region;

a floating gate memory cell formed on each active region and corresponding to the fin of that active region, the memory cell comprising;

a tunnel dielectric layer formed on the active region, including the fin of that active region;

a floating gate formed on a portion of the tunnel dielectric layer;

an intergate dielectric layer formed on the floating gate and on a portion of the tunnel dielectric layer on which there is no floating gate; and

a control gate layer formed on the intergate dielectric layer;

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of every other row of memory cells faces a first direction; and

wherein the floating gate formed on the portion of the tunnel dielectric layer of the memory cells of intervening rows of memory cells faces a second direction opposite the first direction.