Vertical electrical device

• US 20080122031A1
• Filed: 07/11/2006
• Published: 05/29/2008
• Est. Priority Date: 07/11/2006
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Rockwell Scientific Licensing LLC (Teledyne Technologies Incorporated)
• Inventors: DeNatale, Jeffrey F., Pettersson, Per-Olov, Lauxtermann, Stefan C.
• Granted Patent: US 7,989,915 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer electrically conductive layer is disposed on the outer wall, with an electrically insulative material disposed between the inner and outer layers. An electrical conductor in the substrate is bounded by the inner electrically conductive layer.

Claims

1. A vertical electrical device, comprising:

a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall;

an inner electrically conductive layer disposed on said inner wall;

an outer electrically conductive layer disposed on said outer wall;

an electrically insulative material disposed between said inner and outer electrically conductive layers; and

an electrical conductor in said substrate and bounded by said inner electrically conductive layer.

2. The device of claim 1, further comprising:

a first electrical connection between said device and a first electronic circuit on a first circuit layer.

3. The device of claim 2, wherein said first electrical connection comprises a first planar conductor connecting said first electronic circuit to said electrical conductor.

4. The device of claim 2, further comprising:

a second electrical connection between said device and a second electronic circuit on a second circuit layer.

5. The device of claim 1, wherein said inner electrically conductive layer comprises an inner electrically conductive metal layer and said outer electrically conductive layer comprises an outer electrically conductive metal layer.

6. The device of claim 1, wherein said electrically insulative material comprises an organic material.

7. The device of claim 6, wherein said organic electrically insulative material comprises parylene.

8. The device of claim 1, wherein said electrically insulative material comprises an inorganic material.

9. The device of claim 8, wherein said electrically insulative material comprises an inorganic material selected from the group consisting of oxides and nitrides.

10. The device of claim 1, wherein said substrate comprises a semiconductive substrate.

11. The device of claim 10, wherein said semiconductive substrate comprises a silicon substrate.

12. The device of claim 1, wherein the region comprises a cylindrical region.

13. The device of claim 1, wherein the electrical conductor and the outer electrically conductive layer extend beyond the substrate at the first surface.

14. The device of claim 13, wherein the electrical conductor and the outer electrically conductive layer extend beyond the substrate at the second surface.

15. The device of claim 1, wherein a portion of the electrical conductor proximate said surface of the substrate is reduced in size relative to the remaining portion of the conductor.

16. The device of claim 1, wherein said insulative material and said outer conductive layer provide high frequency signal isolation for said electrical conductor, the device operable thereby as a high frequency shielded electrical conductor.

17. The device of claim 16, wherein the inner electrically conductive layer, the outer electrically conductive layer, the electrically insulative material, and the electrical conductor are fabricated with dimensions and of materials selected to optimize the radio frequency properties of the device.

19. The device of claim 1, wherein said outer conductive layer comprises a first electrode, said electrical conductor comprises a second electrode, and said electrically insulative material is a dielectric material, the device operable thereby as a coaxial capacitor.

20. The device of claim 19, wherein a portion of the second electrode proximate said surface of the substrate is reduced in size relative to the remaining portion of the electrode.

18. A vertical high frequency shielded electrical conductor, comprising:

a cylindrical region in a semiconductive substrate extending from a first surface of the substrate, the region having an inner wall, an outer wall circumscribing the inner wall, and a bottom surface between the outer and inner walls;

an inner metal electrically conductive layer disposed on said inner wall;

an outer metal electrically conductive layer disposed on said outer wall;

an electrically insulative region disposed between said inner and outer electrically conductive layers and substantially filling the region;

an electrical conductor in said substrate, bounded by said inner electrically conductive layer, and extending through a second surface of said substrate, the electrical conductor thereby forming an electrical interconnect via through said substrate, said insulative region and said outer conductive layer providing high frequency isolation for the electrical interconnect.

21. A vertical coaxial capacitor, comprising:

a region in a semiconductive substrate through a surface of the substrate, the region having an outer wall;

an outer metal electrically conductive layer disposed on said outer wall;

a dielectric material disposed on said outer electrically conductive layer;

an inner metal electrically conductive layer disposed on said dielectric material; and

an electrical conductor in said substrate and bounded by said inner electrically conductive layer, such that said outer conductive layer comprises a first electrode for the capacitor and said electrical conductor comprises a second electrode for the capacitor.

22. The vertical coaxial capacitor of claim 21, wherein the region comprises a first region through a first surface of the substrate, the first region having a first outer wall and a first bottom surface, and a second region into the substrate through a second surface of the substrate, the second region having a second outer wall larger in diameter than the first outer wall and a second bottom surface, such that the second region extends to the first bottom surface;

and wherein the outer metal electrically conductive layer is disposed on said first outer wall, said second outer wall, and said second bottom surface.

23. A method of making a vertical electrical device, comprising:

forming a region into a substrate through a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall;

forming an inner electrically conductive layer on said inner wall and an outer electrically conductive layer on said outer wall;

inserting an electrically insulative material between said inner and outer electrically conductive layers; and

forming an electrical conductor in said substrate and bounded by said inner electrically conductive layer.

24. The method of claim 23, further comprising forming a first electrical connection between the electrical conductor and a first electronic circuit on a first circuit layer.

25. The method of claim 24, wherein forming a first electrical connection comprises forming a first planar conductor connecting the electrical conductor and the first electronic circuit.

26. The method of claim 24, further comprising:

forming a second electrical connection between the electrical conductor and a second electronic circuit on a second circuit layer.

27. The method of claim 23, wherein forming an outer electrically conductive layer comprises plating a metal, electrically conductive layer onto said outer wall.

28. The method of claim 23, wherein forming an outer electrically conductive layer comprises depositing, by atomic layer deposition, an electrically conductive layer onto said outer wall.

29. The method of claim 23, wherein inserting an electrically insulative material between said inner and outer electrically conductive layers comprises depositing a conformal vapor deposited polymer.

30. The method of claim 23, wherein depositing a conformal vapor deposited polymer comprises depositing parylene.

31. The method of claim 23, wherein inserting an electrically insulative material between said inner and outer electrically conductive layers comprises depositing an electrically insulative material by atomic layer deposition.

32. The method of claim 23, wherein inserting an electrically insulative material between said inner and outer electrically conductive layers comprises depositing a curable liquid polymer.

33. The method of claim 23, wherein forming an electrical conductor comprises depositing an electrically conductive material in said substrate.

34. The method of claim 23, wherein the substrate is semiconductive.

35. The method of claim 34, wherein said semiconducting substrate further comprises a semiconducting silicon substrate.

36. The method of claim 23, wherein forming a region into a substrate further comprises forming an annular region into a substrate.

37. The method of claim 36, further comprising, after forming an electrical conductor in said substrate, removing material from said substrate at a second surface of the substrate to expose the conductor at the second surface.

38. The method of claim 37, wherein removing material from said substrate further comprises removing a portion of the substrate reduced in diameter relative to the diameter of the electrical conductor.

39. The method of claim 37, wherein removing material from said substrate comprises removing, by an isotropic etch process, material from said substrate.

40. The method of claim 39, wherein the isotropic etch process is selected from the group consisting of the XeF₂, SF₆, KOH, and TMAH etch processes.

41. The method of claim 37, wherein removing material from said substrate comprises removing, by an anisotropic etch process, material from said substrate.

42. The method of claim 41, wherein the anisotropic etch process is selected from the group consisting of time-sequenced etch/passivate processes using SF6 and C4F8 and cryogenic etch processes.

43. The method of claim 37, wherein removing material from said substrate comprises removing, by an isotropic etch, material from said substrate.

44. The method of claim 43, wherein the isotropic etch is selected from the group consisting of XeF₂, SF₆, etch, KOH, and TMAH.

45. The method of claim 23, further comprising selecting dimensions of and materials for the inner electrically conductive layer, the outer electrically conductive layer, the electrically insulative material, and the electrical conductor to optimize the radio frequency properties of the device, such that the device is operable as a high frequency shielded electrical conductor.

48. The method of claim 23, further comprising forming the outer electrically conductive layer as a first electrode, forming the electrical conductor as a second electrode, and selecting a dielectric material for the electrically insulative material, such that the device is operable as a coaxial capacitor.

46. A method of making a vertical high frequency shielded electrical interconnect in a substrate, comprising:

forming a region into a substrate through a surface of the substrate, the region having an inner wall, an outer wall circumscribing the inner wall, and a bottom surface;

forming an inner electrically conductive layer on said inner wall and an outer electrically conductive layer on said outer wall;

inserting an electrically insulative material between said inner and outer electrically conductive layers;

forming an electrical conductor in said substrate and bounded by said inner electrically conductive layer; and

removing material from said substrate at a second surface of the substrate to expose the conductor at the second surface, said insulative material and said outer conductive layer providing high frequency isolation for said electrical conductor.

47. A method of making a vertical high frequency shielded electrical via in a semiconductive substrate, comprising:

forming a cylindrical region into a semiconductive substrate through a first surface of the substrate, the region having an inner wall, an outer wall circumscribing the inner wall, and a bottom surface between the outer and inner walls;

plating a metal, electrically conductive layer on said inner wall and an outer electrically conductive layer on said outer wall;

depositing parylene between said inner and outer electrically conductive layers to establish an electrically insulative region that substantially fills the region;

isotropically etching into the substrate through the first surface to remove a portion of the substrate circumscribed by the region and within the inner wall;

depositing an electrically conducting material in said substrate and bounded by said inner electrically conductive layer to form an electrical conductor; and

removing material from said substrate at said second surface to expose the electrical conductor at said second surface,

the electrical conductor thereby forming an electrical interconnect via through said substrate, said insulative region and said outer conductive layer providing high frequency isolation for the electrical interconnect.

49. A method of making a vertical coaxial capacitor in a semiconductive substrate, comprising:

forming a cylindrical region into a semiconductive substrate through a first surface of the substrate, the region having an inner wall, an outer wall circumscribing the inner wall, and a bottom surface between the outer and inner walls;

plating an inner metal electrically conductive layer on said inner wall

plating an outer metal electrically conductive layer on said outer wall;

inserting a dielectric material between said inner and outer electrically conductive layers;

depositing an electrical conductor in said substrate and bounded by said inner electrically conductive layer; and

removing material from said substrate at a second surface of the substrate to expose the conductor at the second surface, such that said outer conductive layer comprises a first electrode for the capacitor and said electrical conductor comprises a second electrode for the capacitor.

50. A method of making a vertical electrical device, comprising:

forming a region into a substrate through a surface of the substrate, the region having an outer wall;

forming an outer electrically conductive layer on said outer wall;

forming an electrically insulative layer on said outer electrically conductive layer;

forming an inner electrically conductive layer on said electrically insulative layer; and

forming an electrical conductor in said substrate and bounded by said inner electrically conductive layer.

51. The method of claim 50, wherein forming a region into a substrate comprises forming a first region into a substrate through a first surface of the substrate, the first region having a first outer wall and a first bottom surface;

and further comprising forming a second region into the substrate through a second surface of the substrate, the second region having a second outer wall larger in diameter than the first outer wall and a second bottom surface, such that the second region extends to the first bottom surface; and

wherein forming an outer electrically conductive layer comprises forming an outer electrically conductive layer on said first outer wall, said second outer wall, and said second bottom surface.

52. The method of claim 50, further comprising forming a first electrical connection between the electrical conductor and a first electronic-circuit on a first circuit layer.

53. The method of claim 52, wherein forming a first electrical connection comprises forming a first planar conductor connecting the electrical conductor and the first electronic circuit.

54. The method of claim 52, further comprising:

forming a second electrical connection between the electrical conductor and a second electronic circuit on a second circuit layer.

55. The method of claim 50, wherein forming an outer electrically conductive layer comprises plating a metal, electrically conductive layer onto said outer wall.

56. The method of claim 50, wherein forming an outer electrically conductive layer comprises depositing, by atomic layer deposition, an electrically conductive layer onto said outer wall.

57. The method of claim 50, wherein forming an electrically insulative layer on said outer electrically conductive layer comprises depositing a conformal vapor deposited polymer.

58. The method of claim 50, wherein depositing a conformal vapor deposited polymer comprises depositing parylene.

59. The method of claim 50, wherein forming an electrically insulative layer on said outer electrically conductive layer comprises depositing an electrically insulative material by atomic layer deposition.

60. The method of claim 50, wherein forming an electrically insulative layer on said outer electrically conductive layer comprises depositing a curable liquid polymer.

61. The method of claim 50, wherein forming an electrical conductor comprises depositing an electrically conductive material.

62. The method of claim 50, wherein the substrate is semiconductive.

63. The method of claim 50, wherein said semiconducting substrate further comprises a semiconducting silicon substrate.

64. The method of claim 50, further comprising selecting dimensions of and materials for the inner electrically conductive layer, the outer electrically conductive layer, the electrically insulative layer, and the electrical conductor to optimize the radio frequency properties of the device, such that the device is operable as a high frequency shielded electrical conductor.

67. The method of claim 50, further comprising forming the outer electrically conductive layer as a first electrode, forming the electrical conductor as a second electrode, and selecting a dielectric material for the electrically insulative layer, such that the device is operable as a coaxial capacitor.

65. A method of making a vertical high frequency shielded electrical interconnect in a substrate, comprising:

forming a region into a substrate through a surface of the substrate, the region having an outer wall and a bottom surface;

forming an outer electrically conductive layer on said outer wall;

forming an electrically insulative layer on said outer electrically conductive layer;

forming an inner electrically conductive layer on said electrically insulative layer; and

forming an electrical conductor in said substrate and bounded by said inner electrically conductive layer, said insulative layer and said outer conductive layer providing high frequency isolation for said electrical conductor.

66. A method of making a vertical high frequency shielded electrical via in a semiconductive substrate, comprising:

forming a cylindrical region into a semiconductive substrate through a surface of the substrate, the region having an outer wall;

plating an outer metal, electrically conductive layer on said outer wall;

depositing parylene on said outer electrically conductive layer to establish an electrically insulative layer;

plating an inner metal, electrically conductive layer on said electrically insulative layer; and

depositing an electrical conductor in said substrate and bounded by said inner electrically conductive layer, the electrical conductor thereby forming an electrical interconnect via through said substrate, said insulative layer and said outer conductive layer providing high frequency isolation for the electrical interconnect.

68. A method of making a vertical coaxial capacitor in a semiconductive substrate, comprising:

forming a region into a semiconductive substrate through a first surface of the substrate, the region having an outer wall and a bottom surface;

plating an outer metal, electrically conductive layer on said outer wall;

depositing a parylene dielectric on said outer electrically conductive layer to establish an electrically insulative layer;

plating an inner metal, electrically conductive layer on said electrically insulative layer;

depositing an electrical conductor in said substrate and bounded by said inner electrically conductive layer; and

removing material from said substrate at a second surface of the substrate to expose the electrical conductor at said second surface,

such that said outer conductive layer comprises a first electrode for the capacitor and said electrical conductor comprises a second electrode for the capacitor.

69. A method of making a vertical coaxial capacitor in a semiconductive substrate, comprising:

forming a first region into the substrate through a first surface of the substrate, the first region having a first outer wall and a first bottom surface;

forming a second region into the substrate through a second surface of the substrate, the second region having a second outer wall larger in diameter than the first outer wall and a second bottom surface, such that the second region extends to the first bottom surface;

plating an outer metal, electrically conductive layer on said first outer wall, said second outer wall, and said second bottom surface;

depositing a parylene dielectric on said outer electrically conductive layer to establish an electrically insulative layer;

plating an inner metal, electrically conductive layer on said electrically insulative layer; and

depositing an electrical conductor in said substrate and bounded by said inner electrically conductive layer;

such that said outer conductive layer comprises a first electrode for the capacitor and said electrical conductor comprises a second electrode for the capacitor.