CHIP ANTENNA

• US 20080122722A1
• Filed: 11/23/2007
• Published: 05/29/2008
• Est. Priority Date: 11/22/2006
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: CHANG, Ki Won, Sung, Jae Suk, Seo, Jeong Sik, Park, Hyun Do
• Granted Patent: US 8,054,227 B2
• Time in Patent Office: Days
• US Class Current: 343/860
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/243 with built-in antennas
• CPC Class Codes: H01Q 9/42 with folded element, the folded parts being spaced apart a small fraction of the operating wavelength
• CPC Class Codes: H05K 1/0243 Printed circuits associated with mounted high frequency components
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

There is provided a chip antenna including: a dielectric block; a first conductive pattern formed on at least one surface of the dielectric block to connect to an external feeding part; a second conductive pattern spaced apart from the first conductive pattern at a certain distance so as to be capacitively coupled to the first conductive pattern to act as a radiator, the second conductive pattern having one end connected to an external ground part; and a third conductive pattern spaced apart from the first conductive pattern at a certain distance so as to be capacitively coupled to the first conductive pattern to enable impedance matching of the antenna, the third conductive pattern having one end connected to the external ground part.

Claims

1. A chip antenna comprising:

a dielectric block having opposing top and bottom surfaces and a plurality of side surfaces connecting the top and bottom surfaces;

a first conductive pattern formed on at least one of the surfaces of the dielectric block to connect to an external feeding part;

a second conductive pattern formed on at least one of the surfaces of the dielectric block, the second conductive pattern spaced apart from the first conductive pattern at a certain distance so as to be capacitively coupled to the first conductive pattern to act as a radiator, the second conductive pattern having one end connected to an external ground part; and

a third conductive pattern formed on at least one of the surfaces of the dielectric block, the third conductive pattern spaced apart from the first conductive pattern at a certain distance so as to be capacitively coupled to the first conductive pattern to enable impedance matching of the antenna, the third conductive pattern having a lower end connected to the external ground part,

wherein a coupling capacitance between the first and second conductive patterns is greater than a coupling capacitance between the first and third conductive patterns.

2. The chip antenna of claim 1, wherein the dielectric block is shaped as a rectangular parallelepiped.

3. The chip antenna of claim 2, wherein the first and second conductive patterns define a radiator by capacitive coupling,

wherein the radiator is formed across a first side surface parallel to a longitudinal direction of the dielectric block, the top surface and a second side surface opposing the first side surface of the dielectric block.

4. The chip antenna of claim 3, wherein the first conductive pattern is formed on the first side surface parallel to the longitudinal direction of the dielectric block.

5. The chip antenna of claim 4, wherein the first conductive pattern is formed such that a spacing between the first conductive pattern and the top surface of the dielectric block is smaller than a spacing between the first conductive pattern and the bottom surface of the dielectric block.

6. The chip antenna of claim 5, wherein the first conductive pattern is L-shaped.

7. The chip antenna of claim 5, wherein the first conductive pattern has an upper end in contact with an intersecting line between the first side surface and the top surface of the dielectric block.

8. The chip antenna of claim 3, wherein the second conductive pattern is formed across the second side surface opposing the first side surface of the dielectric block and the top surface thereof.

9. The chip antenna of claim 8, wherein the second conductive pattern has another end spaced apart from the intersecting line between the top surface and the first side surface of the dielectric block.

10. The chip antenna of claim 3, wherein the third conductive pattern is formed on the bottom surface of the dielectric block.

11. The chip antenna of claim 10, wherein the third conductive pattern has the lower end in contact with an intersecting line between the bottom surface and the first side surface of the dielectric body, the third conductive pattern having at least one bending.

12. The chip antenna of claim 3, wherein the first conductive pattern is formed on the first side surface of the dielectric block, and has an L shape such that an upper end of the first conductive pattern is in contact with an intersecting line between the first side surface and the top surface of the dielectric block,

the second conductive pattern is formed across the second side surface opposing the first side surface of the dielectric block and the top surface thereof, the second conductive pattern having another end spaced apart at a certain distance from the intersecting line between the top surface and the first surface of the dielectric block, and

the third conductive pattern is formed on the bottom surface of the dielectric block and has the lower end in contact with an intersecting line between the bottom surface and the first side surface of the dielectric block, the third conductive pattern having at least one bending.