PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores during the running of a graphics application

• US 20080122851A1
• Filed: 10/26/2007
• Published: 05/29/2008
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Lucid Information Technology, Ltd.
• Inventors: Bakalash, Reuven, Remez, Offir, Fogel, Efi
• Granted Patent: US 7,843,457 B2
• Time in Patent Office: Days
• US Class Current: 345/505
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A PC-based computing system employing a bridge chip with a routing unit to distribute geometrical data and graphics commands to multiple GPU-driven pipeline cores during a mode of parallel operation. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU) supported on a motherboard, for executing the OS, graphics applications, drivers and graphics libraries. The routing unit in the bridge chip interfaces with the CPU and the GPU-driven pipeline cores. During the generation and display of each frame of pixel data, the routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface.

Claims

1. A PC-based computing system comprising:

system memory for storing software graphics applications, software drivers and graphics libraries;

an operating system (OS), stored in said system memory;

one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene;

one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;

a central processing unit (CPU) supported on a motherboard, for executing said OS, said graphics applications, said drivers and said graphics libraries;

a CPU bus supported on said motherboard;

a bridge chip supported on said motherboard, and including a routing unit located on said CPU bus;

a display surface for displaying said images by graphically displaying frames of pixel data;

a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to a parallelization mode of operation so that said GPU-driven pipeline cores process data in a parallel manner; and

software multi-pipe drivers, stored in said system memory, and including a GPU driver module allowing said GPU-driven pipeline cores to interact with said OS and said graphic libraries, and a distributed graphic functions control module for configuring said parallelization mode of operation;

wherein said routing unit interfaces said CPU and said GPU-driven pipeline cores;

wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed;

(i) said routing unit routes said stream of geometrical data and graphic commands, or a portion thereof, from said CPU to one or more of said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said routing unit routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface.

2. The PC-based computing system of claim 1, wherein said bridge chip further comprises a control unit for accepting commands from said software multi-pipe drivers, and controlling components within said bridge chip, including said routing unit.

3. The PC-based computing system of claim 1, wherein said bridge chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display on said display surface.

4. The PC-based computing system of claim 1, wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.

5. The PC-based computing system of claim 1, wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

6. The PC-based computing system of claim 1, wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

7. The PC-based computing system of claim 1, wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

8. The PC-based computing system of claim 1, wherein said software multi-pipe drivers coordinate the operation of said GPU-driven pipeline cores so generate a sequence of frames of pixel data for displaying a sequence of images of said 3D object on said display surface.

9. The PC-based computing system of claim 1, wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.

10. The PC-based computing system of claim 1, wherein said parallelization mode of operation is a time division mode of parallel operation.

11. The PC-based computing system of claim 1, wherein said parallelization mode of operation is an image division mode of parallel operation.

12. The PC-based computing system of claim 1, wherein said parallelization mode of operation is an object division mode of parallel operation.

13. The PC-based computing system of claim 12, wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

14. The PC-based computing system of claim 1, wherein said plurality of said GPU-driven pipeline cores are realized on said bridge chip, along with said routing unit, and said bridge chip further includes a control unit for accepting commands from said software multi-pipe drivers, and controlling components within said bridge chip, including said routing unit,

15. The PC-based computing system of claim 1, wherein said bridge chip is a memory bridge chip, and said bridge chip also interfaces with said system memory.

16. The PC-based computing system of claim 1, wherein said plurality of GPU-driven pipeline cores are supported on said bridge chip, and wherein said bridge chip further comprises a display interface for interfacing said display surface with at least one of said GPU-driven pipeline core.

17. The PC-based computing system of claim 1, which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein said plurality of GPU-driven pipeline cores are mounted on said graphics card.

18. The PC-based computing system of claim 1, which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

19. The PC-based computing system of claim 1, which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein two or more of said plurality of GPU-driven pipeline cores are supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

20. The PC-based computing system of claim 1, which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card.

21. The PC-based computing system of claim 1, which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, wherein at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

22. The PC-based computing system of claim 1, which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card.

23. The PC-based computing system of claim 1, which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.