METHOD OF DRIVING MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE AND MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE

• US 20080123389A1
• Filed: 09/14/2007
• Published: 05/29/2008
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Ki-sung, CHO, Woo-yeong, KIM, Du-eung
• Granted Patent: US 7,639,522 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell

Abstract

Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

Claims

1. A method of driving a write data value to a multi-level variable resistive memory device, the method comprising:

applying a write current to a variable resistive memory cell to change the actual resistance of the variable resistive memory cell;

verifying whether the actual resistance resides in an intended resistance window associated with the write data value and generating verification results; and

varying the amount of the write current in accordance with the verification results, and again applying the write current to the variable resistive memory cell.

2. The method of claim 1, wherein the resistance window is defined in relation to a first reference resistance and a second reference resistance.

3. The method of claim 2, wherein the amount of write current is increased when the actual resistance is less than the first reference resistance as indicated by the verification results.

4. The method of claim 3, wherein increasing the amount of write current comprises increasing an amplitude of the write current.

5. The method of claim 3, wherein the increasing the amount of write current comprises increasing a pulse width of the write current.

6. The method of claim 2, wherein the amount of write current is decreased when the actual resistance is greater than the second reference resistance as indicated by the verification results.

7. The method of claim 6, wherein decreasing the amount of write current comprises decreasing an amplitude of the write current.

8. The method of claim 6, wherein the decreasing the amount of write current comprises decreasing a pulse width of the write current.

9. The method of claim 2, further comprising:

iteratively applying the write current, verifying of the actual resistance, varying the amount of write current and reapplication of the write current until the verification results indicate that the actual resistance resides in the intended resistance window as defined by the first and second reference resistances.

10. The method of claim 9, wherein a magnitude of change for the varying of the amount of write current gradually decreases over a number of iterations.

11. The method of claim 9, wherein the number of iterations is stopped when the verification results indicate that the actual resistance resides in the intended resistance window.

12. The method of claim 1, wherein the variable resistive memory cell stores two-bit data.

13. The method of claim 1, wherein the variable resistive memory cell is a phase change memory cell.

14. A multi-level variable resistive memory device, comprising:

a memory cell array including a variable resistive memory cell;

a verification sense amplifier verifying whether the actual resistance of the variable resistive memory cell resides in an intended resistance window and generating verification results;

a write control circuit supplying a control signal to increase or decrease the amount of write current applied to the variable resistive memory cell on the basis of the verification results; and

a write driver supplying the write current to the variable resistive memory cell, and increasing or decreasing the amount of the write current in response to the control signal.

15. The multi-level variable resistive memory device of claim 14, wherein the intended resistance window is defined by a first reference resistance and a second reference resistance.

16. The multi-level variable resistive memory device of claim 15, wherein the write driver increases the amount of the write current when the actual resistance is less than the first reference resistance as indicated by the verification results.

17. The multi-level variable resistive memory device of claim 15, wherein the write driver decreases the amount of the write current when the actual resistance is greater than the second reference resistance as indicated by the verification results.

18. The multi-level variable resistive memory device of claim 15, wherein the verification sense amplifier comprises:

a first sense amplifier sensing the actual resistance of the variable resistive memory cell using a first reference voltage corresponding to the first reference resistance; and

a second sense amplifier sensing the actual resistance of the variable resistive memory cell using a second reference voltage corresponding to the second reference resistance.

19. The multi-level variable resistive memory device of claim 14, wherein the write driver supplies the write current to the variable resistive memory cell through a series of write loops, and the increased or decreased amount of the write current gradually decreases over the series of write loops.

20. The multi-level variable resistive memory device of claim 14, wherein the write driver discontinues supply of the write current to the variable resistive memory cell when the actual resistance resides in the intended resistance window as indicated by the verification results.

21. The multi-level variable resistive memory device of claim 14, wherein the variable resistive memory cell stores two-bit data.

22. The multi-level variable resistive memory device of claim 14, wherein the variable resistive memory cell is a phase change memory cell.