NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME

• US 20080123393A1
• Filed: 12/19/2007
• Published: 05/29/2008
• Est. Priority Date: 06/20/2005
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: KINOSHITA, Kentaro
• Application Number:
  US11/959,781
• Publication Number:
  US 20080123393A1
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, includes the step of applying the voltage to the resistance memory element for switching from the high resistance state to the low resistance state, while a value of a current to flow in the resistance memory elements are limited to thereby memorize in the resistance memory elements the low resistance state of the low resistance value corresponding to the limited value of the current.

Claims

1. A method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, comprising:

applying the voltage to the resistance memory element for switching from the high resistance state to the low resistance state, while a value of a current to flow in the resistance memory element being limited to thereby memorize the low resistance state of a low resistance value corresponding to the limited value of the current.

2. The method of writing into a nonvolatile semiconductor memory device according to claim 1, wherein

the value of the current to flow in the resistance memory element is limited by a resistance value of a variable resistor serially connected to the resistance memory element.

3. The method of writing into a nonvolatile semiconductor memory device according to claim 2, wherein

the variable resistor is a MIS transistor, and

the resistance value of the variable resistor is controlled by a channel resistance of the MIS transistor.

4. The method of writing into a nonvolatile semiconductor memory device according to claim 2, wherein

the variable resistor includes a plurality of resistor parallelly connected, and

the resistance value of the variable resistor is controlled by selecting the resistor connected to the resistance memory element.

5. The method of writing into a nonvolatile semiconductor memory device according to claim 2, further comprising:

applying the voltage to the resistance memory element for switching from the low resistance state to the high resistance state, while the resistance value of the variable resistor is controlled to be sufficiently smaller than a resistance value of the resistance memory element.

6. The method of writing into a nonvolatile semiconductor memory device according to claim 1, wherein

the nonvolatile semiconductor memory device further comprising a select transistor serially connected to the resistance memory element, and

the select transistor includes a channel resistance controlled to be sufficiently smaller than a resistance value of the resistance memory element when the voltage is applied to the resistance memory element to thereby switch the resistance state.

7. The method of writing into a nonvolatile semiconductor memory device according to claim 1, wherein

in memorizing the low resistance state of a first resistance value in the resistance memory element, the value of the current to flow in the resistance memory element is limited to a first current value, and

in memorizing the low resistance state of a second resistance value which is higher than the first resistance value in the resistance memory element, the value of the current to flow in the resistance memory element is limited to a second current value lower than the first current value.

8. The method of writing into a nonvolatile semiconductor memory device according to claim 7, wherein

the value of the current to flow in the resistance memory element is limited by a resistance value of a variable resistor serially connected to the resistance memory element.

9. The method of writing into a nonvolatile semiconductor memory device according to claim 8, wherein

the variable resistor is a MIS transistor, and

the resistance value of the variable resistor is controlled by a channel resistance of the MIS transistor.

10. The method of writing into a nonvolatile semiconductor memory device according to claim 8, wherein

the variable resistor includes a plurality of resistor parallelly connected, and

the resistance value of the variable resistor is controlled by selecting the resistor connected to the resistance memory element.

11. The method of writing into a nonvolatile semiconductor memory device according to claim 8, further comprising:

applying the voltage to the resistance memory element for switching from the low resistance state to the high resistance state, while the resistance value of the variable resistor is controlled to be sufficiently smaller than a resistance value of the resistance memory element.

12. The method of writing into a nonvolatile semiconductor memory device according to claim 7, wherein

the nonvolatile semiconductor memory device further comprising a select transistor serially connected to the resistance memory element, and

the select transistor includes a channel resistance controlled to be sufficiently smaller than a resistance value of the resistance memory element when the voltage is applied to the resistance memory element to thereby switch the resistance state.

13. A nonvolatile semiconductor memory device comprising;

a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage;

a variable resistor serially connected to the resistance memory element; and

a current limitation circuit which, when the voltage is applied to the resistance memory element to switch from the high resistance state to the low resistance stage, a value of a current to flow in the resistance memory element being limited to memorize in the resistance memory element the low resistance state of a low resistance value corresponding to the limited value of the current.

14. The nonvolatile semiconductor memory device according to claim 13, wherein

the variable resistor is a MIS transistor, and

the current limitation circuit controls the resistance value of the variable resistor by a channel resistance of the MIS transistor.

15. The nonvolatile semiconductor memory device according to claim 13, wherein

the variable resistor includes a plurality of resistors parallelly connected, and

the resistor connecting to the resistance memory element is selected by the current limitation circuit to thereby control a resistance value of the variable resistor.

16. A nonvolatile semiconductor memory device comprising:

a plurality of memory cells arranged in a matrix, each including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, and a select transistor having one terminal serially connected to one terminal of the resistance memory element;

a plurality of first signal lines parallelly extended in a first direction and each connected to gate electrodes of the select transistors of the memory cells arranged in the first direction;

a plurality of second signal lines parallelly extended in a second direction intersecting the first direction and each connected to the other terminals of the resistance memory elements of the memory cells arranged in the second direction;

a plurality of third signal lines parallelly extended in the first direction and each connected to the other terminals of the select transistors of the memory cells arranged in the first direction;

variable resistors serially connected to the other terminals of the resistance memory elements; and

a current limitation circuit which, when a voltage is applied to the resistance memory element to switch from the high resistance state to the low resistance state, controls a value of a current to flow in the resistance memory element to thereby memorize in the resistance memory element the low resistance state of a low resistance value corresponding to the limited value of the current.

17. The nonvolatile semiconductor memory device according to claim 16, wherein

the variable resistors are provided one for the respective plurality of second signal lines.

18. The nonvolatile semiconductor memory device according to claim 16, in which

the variable resistors are provided one for the respective plurality of memory cells, and which further comprises

a plurality of fourth signal lines which are parallelly extended in the first direction and each connected to gate electrodes of the variable resistors of the memory cells arranged in the first direction.