Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 20080123418A1
• Filed: 11/29/2007
• Published: 05/29/2008
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 7,760,548 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.

Claims

1. A semiconductor memory cell comprising:

a substrate having a first conductivity type;

a first region embedded in the substrate at a first location of the substrate and having a second conductivity type;

a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory;

a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer;

the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and

a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.

2. The semiconductor memory cell of claim 1, wherein the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type.

3. The semiconductor memory cell of claim 1, wherein the first conductivity type is “

p”

type and the second conductivity type is “

n”

type.

4. The semiconductor memory cell of claim 1, further comprising insulating layers bounding the side surfaces of the substrate.

5. The semiconductor cell of claim 1, wherein the floating body is configured so that data can be written thereto by hot hole injection.

6. The semiconductor memory cell of claim 1, wherein when power to the cell is interrupted, data transfer from the floating body to the floating gate or trapping layer occurs and the floating gate or trapping layer stores the data as non-volatile memory.

7. The semiconductor memory cell of claim 1, wherein the floating gate or trapping layer stores a charge in non-volatile memory that is complementary to a charge that was stored in the floating body at a time when the power is interrupted.

8. The semiconductor memory cell of claim 6, wherein when power is restored to the cell, data transfer from the floating gate or trapping layer to the floating body occurs and the cell functions as volatile memory.

9. The semiconductor memory cell of claim 8, wherein a state of the floating gate or trapping layer is set to a positive state after the data is transferred from the floating gate or trapping layer to the floating body.

10. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a binary cell.

11. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a multi-level cell.

12. A method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

reading and storing data to the floating body while power is applied to the memory cell;

transferring the data stored in the floating body to the floating gate or trapping layer when power to the cell is interrupted; and

storing the data in the floating gate or trapping layer as non-volatile memory.

13. The method of claim 12, wherein the data stored in the floating body is stored as volatile memory.

14. The method of claim 12, further comprising:

transferring the data stored in the floating gate or trapping layer to the floating body when power is restored to the cell;

and storing the data in the floating body as volatile memory.

15. The method of claim 12, wherein the data transferred is stored in the floating gate or trapping layer with a charge that is complementary to a charge of the floating body when storing the data.

16. The method of claim 12, wherein the transferring is a non-algorithmic process.

17. The method of claim 16, wherein the transferring is a parallel, non-algorithmic process.

18. The method of claim 14, wherein the transferring is a non-algorithmic process.

19. The method of claim 14, further comprising restoring the floating gate or trapping layer to a predetermined charge state.

20. The method of claim 14, further comprising writing a predetermined state to the floating body prior to the transferring the data stored in the floating gate or trapping layer to the floating body.

21. The method of claim 20, wherein the predetermined state is state “

0”

.

22. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

reading and storing data to the floating bodies as volatile memory while power is applied to the device;

transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and

storing the data in the floating gates or trapping layers as non-volatile memory.

23. The method of claim 22, further comprising:

transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to the cell;

and storing the data in the floating bodies as volatile memory.

24. The method of claim 22, further comprising initializing the floating gates or trapping layers, to each have the same predetermined state prior to the transferring.

25. The method of claim 24, wherein the predetermined state comprises a positive charge.

26. The method of claim 22, wherein the data transferred is stored in the floating gates or trapping layers with charges that are complementary to charges of the floating bodies when storing the data.

27. The method of claim 23, further comprising restoring the floating gates or trapping layers to a predetermined charge state after the restore process.

28. The method of claim 23, further comprising writing a predetermined state to the floating bodies prior to the transferring the data stored in the floating gates or trapping layers to the floating bodies.

29. The method of claim 28, wherein the predetermined state is state “

0”

.

30. A semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

31. The device of claim 30, wherein data is transferred from the volatile memory to the non-volatile memory by a parallel, non-algorithmic mechanism.

32. The device of claim 30, wherein the device is configured to transfer data stored in non-volatile memory to store the data in the volatile memory when power is restored to the device.

33. The device of claim 32, wherein the data is transferred from the non-volatile memory to the volatile memory by a parallel, non-algorithmic mechanism.