Nonvolatile Memory With Variable Read Threshold

• US 20080123420A1
• Filed: 11/03/2006
• Published: 05/29/2008
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Brandman, Yigal
• Granted Patent: US 7,558,109 B2
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.

Claims

1. A flash memory system comprising:

a flash memory array that includes a plurality of memory cells programmed to a plurality of programmed states;

a reading circuit connected to the memory array, the reading circuit comparing a memory cell threshold voltage to a first plurality of predetermined voltages to distinguish the plurality of programmed states in a first mode and comparing the memory cell threshold voltage to a second plurality of predetermined voltages to distinguish the plurality of programmed states in a second mode, the highest one of the second plurality of predetermined voltages being higher than the highest one of the first plurality of predetermined voltages.

2. The flash memory system of claim 1 further comprising a programming circuit.

3. The flash memory system of claim 2 wherein the programming circuit programs cells to a first plurality of target voltages individually corresponding to programmed states in the first mode and programming cells to a second plurality of target voltages individually corresponding to programmed states in the second mode.

4. The flash memory system of claim 3 further comprising maintaining a record that indicates whether a portion of the memory array was programmed in the first mode or in the second mode.

5. The flash memory system of claim 3 wherein the highest one of the second plurality of target voltages is higher than the highest one of the first plurality of target voltages.

6. The flash memory system of claim 3 wherein the second plurality of target voltages are more widely spaced than the first plurality of target voltages.

7. The flash memory system of claim 1 wherein the reading circuit further distinguishes within individual ones of the plurality of programmed states to provide probability information regarding cell states.

8. The flash memory system of claim 1 further comprising a soft-input soft-output decoder.

9. The flash memory system of claim 8 wherein the flash memory system changes from the first mode to the second mode in response to a signal generated by the soft-input soft-output decoder.

10. The flash memory system of claim 1 further comprising an erase count indicator, and wherein the flash memory system changes from the first mode to the second mode when an erase count maintained by the erase count indicator exceeds a predetermined value.

11. The flash memory system of claim 1 wherein the flash memory system is in a removable memory card having a host interface.

12. A flash memory system comprising:

a memory array that includes a plurality of nonvolatile memory cells;

an ECC decoder that decodes data from the memory array;

a reading circuit connected to the memory array, the reading circuit comparing a threshold voltage of a memory cell to at least one predetermined voltage to determine a programmed state of the memory cell; and

an adjustment circuit that increases or decreases the at least one predetermined voltage in response to information from the ECC decoder.

13. The flash memory system of claim 12 wherein the ECC decoder is a soft-input soft-output decoder.

14. The flash memory system of claim 13 wherein the reading circuit provides a soft-input to the soft-input soft-output decoder.

15. The flash memory system of claim 12 wherein the reading circuit compares the threshold voltage to two predetermined voltages that define a threshold voltage range associated with the programmed state and the adjustment circuit widens the threshold voltage range.

16. The flash memory system of claim 12 further comprising a programming circuit that programs the plurality of nonvolatile memory cells to a plurality of target voltages.

17. The flash memory system of claim 12 wherein the adjustment circuit increases or decreases at least one of the plurality of target voltages in response to information from the ECC decoder.

18. The flash memory of claim 17 wherein the adjustment circuit increases the plurality of target voltages and increases the at least one predetermined voltage together.

19. A flash memory system comprising:

an array of flash memory cells;

a soft-input soft-output decoder;

a reading circuit connected to the memory array and providing an input to the soft-input soft-output decoder, the reading circuit comparing a threshold voltage of a memory cell to a first plurality of predetermined voltages to distinguish the plurality of memory states in a first mode and comparing the threshold voltage of the memory cell to a second plurality of predetermined voltages to distinguish the plurality of memory states in a second mode, the highest one of the second plurality of predetermined voltages being higher than the highest one of the first plurality of predetermined voltages, the second plurality of predetermined voltages determined by corrections performed by the soft-input soft-output decoder.

20. The flash memory system of claim 19 wherein the flash memory system changes from the first mode to the second mode in response to corrections performed by the soft-input soft-output decoder.

21. The flash memory system of claim 19 further comprising a programming circuit that programs flash memory cells to target voltages.

22. The flash memory system of claim 21 wherein the programming circuit programs a plurality of flash memory cells to a first plurality of target voltages in the first mode and programs the plurality of flash memory cells to a second plurality of target voltages in the second mode, the highest one of the second plurality of target voltages being higher than the highest one of the first plurality of target voltages.

23. The flash memory system of claim 22 further comprising an indicator that indicates whether a portion of the memory array was programmed in the first mode or in the second mode.