NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES FOR REDUCED PROGRAM DISTURB

• US 20080123426A1
• Filed: 11/02/2006
• Published: 05/29/2008
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lutze, Jeffrey W., Dong, Yingda
• Granted Patent: US 7,468,911 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

A non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

Claims

1. A non-volatile storage system, comprising:

a set of non-volatile storage elements;

a plurality of word lines in communication with set of non-volatile storage elements, at least one storage element communicates with a selected word line of the plurality of word lines; and

one or more control circuits in communication with the set of non-volatile storage elements, the one or more control circuits program the at least one storage element and during the programming, apply a first set of voltages to unselected word lines of the plurality of word lines and switch, based on a boosting mode switching criterion, from applying the first set of voltages to applying a second set of voltages to the unselected word lines, the first set of voltages varying from the second set of voltages, at least in part.

2. The non-volatile storage system of claim 1, wherein:

the one or more control circuits program the at least one storage element by applying a pulse train to the selected word line, the switching occurs after a first pulse in the pulse train is applied and before a last pulse in the pulse train is applied.

3. The non-volatile storage system of claim 1, wherein:

the one or more control circuits program the at least one storage element by applying a pulse train to the selected word line, the boosting mode switching criterion is based on when a program pulse of a specified amplitude in the pulse train is applied to the selected word line.

4. The non-volatile storage system of claim 1, wherein:

the one or more control circuits program the at least one storage element by applying a pulse train to the selected word line, the boosting mode switching criterion is based on when a specified number of program pulses in the pulse train have been applied to the selected word line.

5. The non-volatile storage system of claim 1, wherein:

the boosting mode switching criterion is based on a position of the selected word line among the plurality of word lines.

6. A non-volatile storage system, comprising:

a set of non-volatile storage elements; and

one or more control circuits in communication with the set of non-volatile storage elements, the one or more control circuits implement a first boosting mode during a first programming phase in which programming of at least one storage element in the set of non-volatile storage elements occurs, and implement a second boosting mode during a second programming phase in which programming of the at least one storage element continues.

7. The non-volatile storage system of claim 6, wherein:

a threshold voltage of the at least one storage element is increased from a first level to a second level during the first programming phase, and from the second level to a third level during the second programming phase.

8. The non-volatile storage system of claim 6, wherein:

the first programming phase comprises a first pass of a multi-pass programming technique and the second programming phase comprises a second pass of the multi-pass programming technique.

9. The non-volatile storage system of claim 6, wherein:

in the first programming phase, a first subset of pulses in a pulse train is applied to the at least one storage element and, in the second programming phase, a second subset of pulses in the pulse train is applied to the at least one storage element.

10. The non-volatile storage system of claim 6, wherein:

in the first programming phase, a first pulse train is applied to the at least one storage element and, in the second programming phase, a second pulse train is applied to the at least one storage element.

11. The non-volatile storage system of claim 6, wherein:

the first programming phase involves coarse programming and the second programming phase involves fine programming.

12. The non-volatile storage system of claim 6, wherein:

the one or more control circuits switch from implementing the first boosting mode to implementing the second boosting mode based on when at least one other storage element in the set of non-volatile storage elements reaches a specified programming condition.

13. The non-volatile storage system of claim 6, wherein:

the one or more control circuits switch from implementing the first boosting mode to implementing the second boosting mode based on a number of programming cycles experienced by the set of non-volatile storage elements.

14. The non-volatile storage system of claim 6, wherein:

the set of non-volatile storage elements are provided in a plurality of NAND strings, including a selected NAND string in which the at least one storage element is provided, and an unselected NAND string, the first and second boosting modes boost a channel of the unselected NAND string.

15. The non-volatile storage system of claim 14, wherein:

the one or more control circuits implement the first boosting mode by boosting the channel without isolating a portion of the channel on a source-side of the unselected NAND string from a portion of the channel on a drain-side of the unselected NAND string; and

the one or more control circuits implement the second boosting mode by isolating a portion of the channel on a source-side of the unselected NAND string from a portion of the channel on a drain-side of the unselected NAND string.

16. The non-volatile storage system of claim 14, wherein:

the one or more control circuits implement the first boosting mode by boosting the channel without isolating a portion of the channel on a programmed side of the unselected NAND string from a portion of the channel on an erased side of the unselected NAND string; and

the one or more control circuits implement the second boosting mode by isolating a portion of the channel on a programmed side of the unselected NAND string from a portion of the channel on an erased side of the unselected NAND string.

17. The non-volatile storage system of claim 14, wherein:

the one or more control circuits implement the first boosting mode by applying a first voltage to an end word line associated with the unselected NAND string, and the one or more control circuits implement the second boosting mode by applying a second voltage to the end word line.

18. A non-volatile storage system, comprising:

a set of non-volatile storage elements;

a plurality of word lines in communication with the set of non-volatile storage elements, at least one storage element communicates with a selected word line of the plurality of word lines; and

one or more control circuits in communication with the set of non-volatile storage elements, the one or more control circuits program the at least one storage element by applying a pulse train to the selected word line during the programming, implement a first boosting mode for unselected non-volatile storage elements in the set of non-volatile storage elements when a first subset of program pulses in the pulse train is applied to the selected word line, and switch from implementing the first boosting mode to implementing a second boosting mode for the unselected non-volatile storage elements when a second subset of program pulses in the pulse train is applied to the selected word line.

19. The non-volatile storage system of claim 18, wherein:

the switching occurs based on when a program pulse of a specified amplitude in the pulse train is applied to the selected word line.

20. The non-volatile storage system of claim 18, wherein:

the switching occurs based on when a specified number of program pulses in the pulse train have been applied to the selected word line.

21. The non-volatile storage system of claim 18, wherein:

the switching occurs based on a position of the selected word line among the plurality of word lines.

22. The non-volatile storage system of claim 18, wherein:

the one or more control circuits implement the first boosting mode by applying a first set of voltages to unselected word lines of the plurality of word lines which are in communication with the unselected non-volatile storage elements, and implement the second boosting mode by applying a second set of voltages to the unselected word lines, the first set of voltages varying from the second set of voltages, at least in part.

23. The non-volatile storage system of claim 22, wherein:

the voltages in the second set are elevated relative to the voltages in the first set, at least in part.

24. The non-volatile storage system of claim 18, wherein:

the set of non-volatile storage elements are provided in a plurality of NAND strings, including a selected NAND string in which the at least one storage element is provided, and an unselected NAND string, the first and second boosting modes boost a channel of the unselected NAND string.

25. The non-volatile storage system of claim 24, wherein:

the one or more control circuits implement the first boosting mode by boosting the channel without isolating a portion of the channel on a source-side of the unselected NAND string from a portion of the channel on a drain-side of the unselected NAND string; and

the one or more control circuits implement the second boosting mode by isolating a portion of the channel on a source-side of the unselected NAND string from a portion of the channel on a drain-side of the unselected NAND string.

26. The non-volatile storage system of claim 24, wherein:

the one or more control circuits implement the first boosting mode by boosting the channel without isolating a portion of the channel on a programmed side of the unselected NAND string from a portion of the channel on an erased side of the unselected NAND string; and

the one or more control circuits implement the second boosting mode by isolating a portion of the channel on a programmed side of the unselected NAND string from a portion of the channel on an erased side of the unselected NAND string.