FLASH MEMORY DEVICE AND PROGRAMMING METHOD OF FLASH MEMORY DEVICE
First Claim
1. A programming method of a flash memory, comprising:
- selecting bit lines connected to program cells of a plurality of memory cells coupled to a selected word line;
driving the selected bit lines to a bit line program voltage through a write driver connected to first ends of the selected bit lines; and
driving the selected bit lines to the bit line program voltage through a bit line detecting/driving circuit connected to second ends of the selected bit lines,wherein the bit line detecting/driving circuit activates the selected bit lines synchronously with voltage variations of the selected bit lines.
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Abstract
A flash memory device and a method of programming a flash memory device include selecting bit lines connected to program cells of multiple memory cells coupled to a selected word line. The selected bit lines are driven to a bit line program voltage through a write driver circuit connected to first ends of the selected bit lines. The selected bit lines are also driven to the bit line program voltage through a bit line detecting/driving circuit connected to second ends of the selected bit lines. The bit line detecting/driving circuit activates the selected bit lines synchronously with voltage variations of the selected bit lines.
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Citations
22 Claims
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1. A programming method of a flash memory, comprising:
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selecting bit lines connected to program cells of a plurality of memory cells coupled to a selected word line; driving the selected bit lines to a bit line program voltage through a write driver connected to first ends of the selected bit lines; and driving the selected bit lines to the bit line program voltage through a bit line detecting/driving circuit connected to second ends of the selected bit lines, wherein the bit line detecting/driving circuit activates the selected bit lines synchronously with voltage variations of the selected bit lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A flash memory device comprising:
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a memory cell array comprising a plurality of memory cells configured to connect to a plurality of word lines and a plurality of bit lines; a column decoder for selecting at least one bit line of the plurality of bit lines connected to at least one memory cell coupled to a selected word line in response to column selection information; a write driver circuit comprising a plurality of write drivers, at least one write driver being connected to a first end of the at least one selected bit line; and a bit line detecting/driving circuit comprising a plurality of bit line detector/drivers, at least one bit line detector/driver being connected to a second end of the at least one selected bit line in accordance with the column selection information during a programming operation, wherein the at least one bit line detector/driver detects voltage variations of the corresponding at least one selected bit line and drives the at least one selected bit line in accordance with a result of the detection. - View Dependent Claims (10, 11, 12, 13)
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14. A flash memory device comprising:
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a memory cell array comprising a plurality of memory cells arranged in a matrix comprising a plurality of word lines and a plurality of bit lines; a column decoder for selecting at least one bit line of the plurality of bit lines in response to a column address; a write driver circuit for driving the at least one selected bit line to a bit line voltage in accordance with input data in response to an enable signal; and a bit line detecting/driving circuit for driving the at least one selected bit line to the bit line voltage synchronously with voltage variations of the at least one selected bit line, in response to a decoding result of the column address during a programming operation. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A flash memory device comprising:
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a memory cell array comprising a plurality of memory cells arranged in a matrix comprising a plurality of word lines and a plurality of bit lines; a first column gate for selecting at least one bit line of the plurality of bit lines in response to column selection information; a first write driver for driving the at least one selected bit line to a bit line voltage in accordance with input data in response to an enable signal; a second column gate for selecting the at least one bit line of the plurality of bit lines in response to the column selection information; and a second write driver for driving the at least one selected bit line to the bit line voltage in accordance with the input data in response to the enable signal, wherein the first write driver is connectable to a first end of the at least one selected bit line through the first column gate and the second write driver is connectable to a second end of the at least one selected bit line through the second column gate.
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Specification