FLASH MEMORY DEVICE AND PROGRAMMING METHOD OF FLASH MEMORY DEVICE

• US 20080123431A1
• Filed: 10/12/2007
• Published: 05/29/2008
• Est. Priority Date: 11/23/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: LEE, Dong-Woo, CHOI, Jong-In
• Granted Patent: US 7,768,837 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

A flash memory device and a method of programming a flash memory device include selecting bit lines connected to program cells of multiple memory cells coupled to a selected word line. The selected bit lines are driven to a bit line program voltage through a write driver circuit connected to first ends of the selected bit lines. The selected bit lines are also driven to the bit line program voltage through a bit line detecting/driving circuit connected to second ends of the selected bit lines. The bit line detecting/driving circuit activates the selected bit lines synchronously with voltage variations of the selected bit lines.

Claims

1. A programming method of a flash memory, comprising:

selecting bit lines connected to program cells of a plurality of memory cells coupled to a selected word line;

driving the selected bit lines to a bit line program voltage through a write driver connected to first ends of the selected bit lines; and

driving the selected bit lines to the bit line program voltage through a bit line detecting/driving circuit connected to second ends of the selected bit lines,

wherein the bit line detecting/driving circuit activates the selected bit lines synchronously with voltage variations of the selected bit lines.

2. The programming method as set forth in claim 1, further comprising:

applying a program voltage to the selected word line coupled to the program cells.

3. The programming method as set forth in claim 2, wherein the program voltage applied to the selected word line is 9˜

11V.

4. The programming method as set forth in claim 1, further comprising:

discharging the bit lines before selecting the bit lines.

5. The programming method as set forth in claim 1, further comprising:

electrically connecting the selected bit lines between the write driver and the bit line detecting/driving circuit.

6. The programming method as set forth in claim 1, further comprising:

maintaining an output of the bit line detecting/driving circuit at a ground voltage after a programming operation.

7. The programming method as set forth in claim 1, wherein the bit line program voltage is 4˜

6V.

8. The programming method as set forth in claim 1, wherein the flash memory comprises a NOR-flash memory.

9. A flash memory device comprising:

a memory cell array comprising a plurality of memory cells configured to connect to a plurality of word lines and a plurality of bit lines;

a column decoder for selecting at least one bit line of the plurality of bit lines connected to at least one memory cell coupled to a selected word line in response to column selection information;

a write driver circuit comprising a plurality of write drivers, at least one write driver being connected to a first end of the at least one selected bit line; and

a bit line detecting/driving circuit comprising a plurality of bit line detector/drivers, at least one bit line detector/driver being connected to a second end of the at least one selected bit line in accordance with the column selection information during a programming operation,

wherein the at least one bit line detector/driver detects voltage variations of the corresponding at least one selected bit line and drives the at least one selected bit line in accordance with a result of the detection.

10. The flash memory device as set forth in claim 9, wherein the write driver circuit and the bit line detecting/driving circuit are connectable to two or more bit lines.

11. The flash memory device as set forth in claim 9, wherein the at least one write driver applies a bit line voltage to the at least one selected bit line in response to an enabling signal.

12. The flash memory device as set forth in claim 11, wherein the enabling signal is activated after activation of the column selection information.

13. The flash memory device as set forth in claim 9, wherein the memory device comprises a NOR-flash memory device.

14. A flash memory device comprising:

a memory cell array comprising a plurality of memory cells arranged in a matrix comprising a plurality of word lines and a plurality of bit lines;

a column decoder for selecting at least one bit line of the plurality of bit lines in response to a column address;

a write driver circuit for driving the at least one selected bit line to a bit line voltage in accordance with input data in response to an enable signal; and

a bit line detecting/driving circuit for driving the at least one selected bit line to the bit line voltage synchronously with voltage variations of the at least one selected bit line, in response to a decoding result of the column address during a programming operation.

15. The flash memory device as set forth in claim 14, wherein the write driver circuit is connected to a first end of the at least one selected bit line and the bit line detecting/driving circuit is connected to a second end of the at least one selected bit line.

16. The flash memory device as set forth in claim 14, wherein the bit line detecting/driving circuit comprises:

a switch circuit for connecting the at least one bit line of the plurality of bit lines in response to the decoding result of the column address; and

a plurality of bit line detector/driver units, at least one bit line detector/driver unit being connected to the at least one selected bit line through the switch circuit, the bit line detecting/driving unit detecting voltages from the at least one bit line and driving the at least one selected bit line to the bit line voltage in accordance with the detected voltages.

17. The flash memory device as set forth in claim 16, wherein the bit line detector/driver units are configured to output low-level voltages at the end of the programming operation.

18. The flash memory device as set forth in claim 16, wherein each of the bit line detecting/driving units comprises:

a PMOS transistor connected between the bit line voltage and an output terminal;

an NMOS transistor connected between the output terminal and a ground voltage, the NMOS transistor being controlled by a control signal from a controller; and

a detector configured to detect voltage variation of the output terminal and to control the PMOS transistor in response to the voltage variation detection.

19. The flash memory device as set forth in claim 18, wherein the detector comprises an inverter.

20. The flash memory device as set forth in claim 18, wherein the control signal is complementary to the decoding result of the column address.

21. The flash memory device as set forth in claim 20, wherein the decoding result of the column address is activated before activation of the enable signal.

22. A flash memory device comprising:

a memory cell array comprising a plurality of memory cells arranged in a matrix comprising a plurality of word lines and a plurality of bit lines;

a first column gate for selecting at least one bit line of the plurality of bit lines in response to column selection information;

a first write driver for driving the at least one selected bit line to a bit line voltage in accordance with input data in response to an enable signal;

a second column gate for selecting the at least one bit line of the plurality of bit lines in response to the column selection information; and

a second write driver for driving the at least one selected bit line to the bit line voltage in accordance with the input data in response to the enable signal,

wherein the first write driver is connectable to a first end of the at least one selected bit line through the first column gate and the second write driver is connectable to a second end of the at least one selected bit line through the second column gate.