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COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS

  • US 20080123459A1
  • Filed: 10/26/2006
  • Published: 05/29/2008
  • Est. Priority Date: 07/31/2006
  • Status: Active Grant
First Claim
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1. A method performed by an electronic system including a plurality of physical memory circuits, the method comprising:

  • identifying at least one of the physical memory circuits; and

    in response to the identifying of the at least one of the physical memory circuits,performing a power saving operation, anddelaying communication of a signal to the identified at least one of the physical memory circuits.

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