COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS

• US 20080123459A1
• Filed: 10/26/2006
• Published: 05/29/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 9,047,976 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.

Claims

1. A method performed by an electronic system including a plurality of physical memory circuits, the method comprising:

identifying at least one of the physical memory circuits; and

in response to the identifying of the at least one of the physical memory circuits,

performing a power saving operation, and

delaying communication of a signal to the identified at least one of the physical memory circuits.

2. The method of claim 1, wherein:

delaying communication of the signal is for a fixed amount of time.

3. The method of claim 1, wherein:

delaying communication of the signal is for a variable amount of time.

4. The method of claim 1, wherein the signal is associated with an operation, wherein the operation comprises at least one of:

a write operation;

a read operation;

a refresh operation;

a mode register write operation;

a mode register read operation;

an activate operation; and

a precharge operation.

5. The method of claim 4, wherein delaying communication of the signal comprises:

delaying communication of the signal for a fixed period of time.

6. The method of claim 4, wherein delaying communication of the signal comprises:

delaying communication of the signal for a variable period of time.

7. The method of claim 1, wherein:

the delaying communication of the signal is associated with a second signal;

wherein the second signal comprises one of an address signal and a control signal.

8. The method of claim 1, wherein:

the delaying communication of the signal is associated with a second signal;

wherein the second signal comprises a data signal.

9. The method of claim 1, wherein:

the delaying communication of the signal is associated with a data signal and at least one of an address signal and a control signal.

10. The method of claim 9 further comprising:

receiving the at least one of an address signal and a control signal from the electronic system; and

receiving the data signal from at least one of the physical memory circuits.

11. The method of claim 1, wherein:

delaying communication of the signal is performed as a function of the signal.

12. The method of claim 1, wherein:

delaying communication of the signal is performed as a function of a previous signal.

13. The method of claim 1, wherein performing the power saving operation comprises:

the identifying including identifying at least one portion of the physical memory circuits that is not currently being accessed;

in response to the identifying at least one portion, initiating the power saving operation upon the at least one portion of the physical memory circuits that is not currently being accessed.

14. The method of claim 13, wherein the identifying at least one portion comprises:

determining whether the at least one portion is being accessed.

15. The method of claim 1, wherein performing the power saving operation comprises:

performing a power down operation.

16. The method of claim 15, wherein performing the power down operation comprises:

performing a precharge power down operation.

17. The method of claim 1, further comprising:

initiating the power saving operation by utilizing an enable pin of the physical memory circuits.

18. The method of claim 17, wherein utilizing the enable pin comprises:

utilizing a clock enable pin.

19. A memory apparatus for use with a system, the memory apparatus comprising:

a plurality of memory circuits;

a component coupled in communication with the plurality of memory circuits and operable to identify at least one of the memory circuits, delay communication of a signal to an identified memory circuit, and perform a power saving operation in association with delayed communication of the signal.

20. The memory apparatus of claim 19, wherein the power saving operation comprises:

a power down operation.