Method of forming T- or gamma-shaped electrode

• US 20080124852A1
• Filed: 11/28/2006
• Published: 05/29/2008
• Est. Priority Date: 11/29/2005
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Mun, Jae Kyoung, Ji, Hong Gu, Chang, Woo Jin, Ahn, Ho Kyun, Lim, Jong Won, Kim, Hae Cheon
• Application Number:
  US11/605,508
• Publication Number:
  US 20080124852A1
• Time in Patent Office: Days
• US Class Current: 438/182
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 21/28593 asymmetrical sectional shape
• CPC Class Codes: H01L 29/4232 with insulated gate

Abstract

A method of forming a fine T- or gamma-shaped gate electrode is provided, which is performed by a lithography process using a multi-layered photoresist layer having various sensitivities, deposition of an insulating layer, and an etching process. The method includes: a first step of depositing a first insulating layer on a semiconductor substrate; a second step of coating at least two photoresist layers with different sensitivities from each other on the first insulating layer, and patterning the photoresist layers to have openings which are different in size; a third step of etching the first insulating layer using the photoresist layers as etch masks to form a step hole in which a part contacting the substrate is narrower than an upper part thereof, and removing the photoresist layers; a fourth step of forming a photoresist layer on the first insulating layer, and forming an opening in the photoresist layer to have a T- or gamma-shaped gate head pattern; a fifth step of performing a gate recess process with respect to the gate pattern; and a sixth step of depositing a gate metal on the gate pattern, and removing the photoresist layers.

Claims

1. A method of forming a T- or gamma-shaped gate electrode, comprising:

a first step of depositing a first insulating layer on a semiconductor substrate;

a second step of coating at least two photoresist layers with different sensitivities from each other on the first insulating layer, and patterning the photoresist layers to have openings which are different in size;

a third step of etching the first insulating layer using the photoresist layers as etch masks to form a step hole in which a part contacting the substrate is narrower than an upper part thereof, and removing the photoresist layers;

a fourth step of forming a photoresist layer on the first insulating layer, and forming an opening in the photoresist layer to have a T- or gamma-shaped gate head pattern;

a fifth step of performing a gate recess process with respect to the gate pattern; and

a sixth step of depositing a gate metal on the gate pattern, and removing the photoresist layers.

2. The method according to claim 1, wherein the thickness of the first insulating layer is adjusted to adjust the height of a gate foot.

3. The method according to claim 1, wherein the first insulating layer comprises at least one layer.

4. The method according to claim 1, wherein the photoresist layer coated in the second step comprises first and second photoresist layers, the first photoresist layer contacting the first insulating layer is formed of polymethyl methacrylate (PMMA) or ZEP, and the second photoresist layer contacting the first photoresist layer is formed of methyl methacrylate-co-methacrylic acid polymer (MMA-MAA) or polymethylglutarimide (PMGI).

5. The method according to claim 4, wherein the openings of the first and second photoresist layers have a size ratio of 1:

1.2 to 1;

3.

6. The method according to claim 4, wherein the lower part of the step hole has a width equal to the opening of the first photoresist layer, and the upper part of the step hole has a width equal to the opening of the second photoresist layer.

7. The method according to claim 1, wherein the photoresist layer coated in the second step comprises first and second photoresist layers, the first photoresist layer contacting the first insulating layer is formed of MMA-MAA or PMGI, and the second photoresist layer contacting the first photoresist layer is formed of PMMA or ZEP.

8. The method according to claim 7, wherein the openings of the first and second photoresist layers have a size ratio of 1:

0.3 to 1;

0.8.

9. The method according to claim 7, wherein the lower part of the step hole has a width equal to the opening of the second photoresist layer, and the upper part of the step hole has a width equal to the opening of the first photoresist layer.

10. The method according to claim 1, wherein the photoresist layer in the fourth step comprises at least one layer, and has a bar-shaped gate head pattern.

11. The method according to claim 1, wherein the photoresist layer in the fourth step comprises at least two layers, and the lower photoresist layer has an opening smaller than that of the upper photoresist layer, thereby forming a T- or gamma-shaped gate head pattern whose tipper part is wider than the lower part.

12. The method according to claim 1, further comprising the steps of:

after the third step,

depositing a second insulating layer on the first insulating layer, and etching back the second insulating layer to partially expose the semiconductor substrate and remain the second insulating layer on a wall of the step hole.