Method for Forming Contact Hole in Semiconductor Device

• US 20080124876A1
• Filed: 09/28/2007
• Published: 05/29/2008
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: RYU, SANG WOOK
• Granted Patent: US 7,524,751 B2
• Time in Patent Office: Days
• US Class Current: 438/296
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Claims

1. A method for forming a contact hole in a semiconductor device, comprising:

forming an isolation layer in a semiconductor substrate to define an active region and a field region;

forming a contact hole exposing at least a portion of the active region and at least a portion of the isolation layer; and

forming a silicon compensation part at an over-etched portion of the isolation layer wherein the silicon compensation part covers the over-etched portion of the isolation layer.

2. The method according to claim 1, wherein forming a silicon compensation part comprises using a Selective Epitaxial Growth (SEG) method.

3. The method according to claim 2, wherein the SEG method comprises the use of silicon (Si), germaniuim (Ge), or Si—

Ge.

4. The method according to claim 2, wherein the SEG method comprises using S_xH_yC_z gas at a rate of about 10 SCCM to about 1,000 SCCM at a pressure of about 10 Torr to about 200 Torr and at a temperature of about 600°

C. to about 900°

C., where x is a positive integer, y is a positive integer, and z is 0 or a positive integer.

5. The method according to claim 4, wherein x is 1, y is 4, and z is 0.

6. The method according to claim 4, wherein x is 2, y is 6, and z is 0.

7. The method according to claim 4, wherein x is 1, y is 2, and z is 12.

8. The method according to claim 1, wherein forming a silicon compensation part comprises:

forming a silicon layer by using a Chemical Vapor Deposition (CVD) method; and

etching the silicon layer to form the silicon compensation part.

9. The method according to claim 8, wherein forming a silicon layer comprises the use of Si, Ge, or Si—

Ge.

10. The method according to claim 1, wherein the at least a portion of the active region comprises a source area.

11. The method according to claim 1, wherein the at least a portion of the active region comprises a drain area.

12. The method according to claim 1, further comprising forming a nitride layer and an interlayer dielectric layer on the semiconductor substrate, wherein forming a contact hole comprises performing a dry etching process with respect to the interlayer dielectric layer and the nitride layer.

13. The method according to claim 12, wherein the dry etching process uses at least one etching gas and at least one additional gas, and wherein the at least one additional gas is oxygen (O₂), nitrogen (N₂), argon (Ar), or helium (He), and wherein the at least one etching gas is C_xH_yF₂, where x is a positive integer, y is a positive integer, and z is a positive integer.

14. The method according to claim 1, further comprising forming a silicide layer on the semiconductor substrate.

15. The method according to claim 14, further comprising:

forming a gate oxide layer, a gate, and a sidewall spacer on the active region;

forming a source/drain area on the active region;

forming a silicide layer on the source/drain area;

forming a nitride layer on the semiconductor substrate including the silicide layer, the isolation layer, the gate, and the sidewall spacer, and

forming an interlayer dielectric layer on the nitride layer;

16. The method according to the claim 15, wherein the nitride layer has a thickness of about 150 Å

to about 800 Å

.

17. The method according to claim 15, wherein the interlayer dielectric layer comprises Phosphorus Silicate Glass (PSG), Boron Phosphorus Silicate Glass (BPSG), or plasma-enhanced tetra ethyl oxysilane (PE-TEOS).